hal_xc_auto.h

gumstiz u-boot loader in linux

#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MSB    12
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_LSB    12
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_DEFAULT    0x00000000
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MASK    0x00000800
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_SHIFT    11
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MSB    11
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_LSB    11
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_DEFAULT    0x00000000
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MASK    0x00000400
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_SHIFT    10
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MSB    10
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_LSB    10
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_DEFAULT    0x00000000
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MASK    0x00000200
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_SHIFT    9
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MSB    9
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_LSB    9
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ)
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_DEFAULT    0x00000000
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MASK    0x00000100
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_SHIFT    8
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MSB    8
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_LSB    8
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ)
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_DEFAULT    0x00000000
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MASK    0x00000080
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_SHIFT    7
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MSB    7
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_LSB    7
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ)
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_DEFAULT    0x00000000
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MASK    0x00000040
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_SHIFT    6
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MSB    6
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_LSB    6
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ)
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_DEFAULT    0x00000000
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MASK    0x00000020
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_SHIFT    5
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MSB    5
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_LSB    5
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ)
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_DEFAULT    0x00000000
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MASK    0x00000010
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_SHIFT    4
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MSB    4
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_LSB    4
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ)
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_DEFAULT    0x00000000
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MASK    0x00000008
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_SHIFT    3
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MSB    3
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_LSB    3
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ)
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_DEFAULT    0x00000000
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MASK    0x00000004
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_SHIFT    2
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MSB    2
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_LSB    2
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ)
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_DEFAULT    0x00000000
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MASK    0x00000002
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_SHIFT    1
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MSB    1
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_LSB    1
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ)
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_DEFAULT    0x00000000
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MASK    0x00000001
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_SHIFT    0
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MSB    0
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_LSB    0
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ)
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_DEFAULT    0x00000000

/* ================================================================
 * Field info for register XC_XCVR_CNTL_INTERRUPT_MASK */
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK    0x00002000
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT    13
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB    13
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB    13
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT    0x00000001
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK    0x00001000
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT    12
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB    12
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB    12
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT    0x00000001
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK    0x00000800
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT    11
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB    11
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB    11
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT    0x00000001
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK    0x00000400
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT    10
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB    10
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB    10
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT    0x00000001
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK    0x00000200
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT    9
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB    9
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB    9
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT    0x00000001
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK    0x00000100
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT    8
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB    8
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB    8
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT    0x00000001
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK    0x00000080
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT    7
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB    7
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB    7
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT    0x00000001
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK    0x00000040
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT    6
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB    6
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB    6
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT    0x00000001
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK    0x00000020
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT    5
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB    5
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB    5
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT    0x00000001
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK    0x00000010
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT    4
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB    4
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB    4
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT    0x00000001
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK    0x00000008
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT    3
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB    3
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB    3
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT    0x00000001
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK    0x00000004
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT    2
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB    2
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB    2
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT    0x00000001
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK    0x00000002
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT    1
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB    1
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB    1
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT    0x00000001
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK    0x00000001
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT    0
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB    0
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB    0
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT    0x00000001

/* ================================================================
 * Field info for register XC_XCVR_CNTL_SCRATCH */
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MASK    0xffffffff
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_SHIFT    0
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MSB    31
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_LSB    0
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE)
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_DEFAULT    0x00000000

/* ================================================================
 * Field info for register XC_XCVR_CNTL_SCRATCH_MASK */
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MASK    0xffffffff
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT    0
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MSB    31
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_LSB    0
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT    0xffffffff

#endif /* matches #ifndef HAL_XC_AUTO_H */