📄 at91sam7l64.h
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#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register
#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register
#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register
#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register
#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register
#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register
#define SDC_FSMR (AT91_CAST(AT91_REG *) 0x00000070) // (SDC_FSMR) Fast Startup Mode Register
#endif
// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock
#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output
// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
// -------- CKGR_PLLR : (PMC Offset: 0x28) PLL A Register --------
// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection
#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected
#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected
#define AT91C_PMC_CSS_PLL_CLK (0x2) // (PMC) Clock from PLL is selected
#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
#define AT91C_PMC_MAINSELS (0x1 << 0) // (PMC) Main Clock Selection Status/Enable/Disable/Mask
#define AT91C_PMC_LOCK (0x1 << 1) // (PMC) PLL Status/Enable/Disable/Mask
#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Reset Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_RSTC {
AT91_REG RSTC_RCR; // Reset Control Register
AT91_REG RSTC_RSR; // Reset Status Register
AT91_REG RSTC_RMR; // Reset Mode Register
} AT91S_RSTC, *AT91PS_RSTC;
#else
#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register
#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register
#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register
#endif
// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset
#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset
#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset
#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password
// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status
#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status
#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type
#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured.
#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level
#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.
// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable
#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable
#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length
#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Supply Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SUPC {
AT91_REG SUPC_CR; // Control Register
AT91_REG SUPC_BOMR; // Brown Out Mode Register
AT91_REG SUPC_MR; // Mode Register
AT91_REG SUPC_WUMR; // Wake Up Mode Register
AT91_REG SUPC_WUIR; // Wake Up Inputs Register
AT91_REG SUPC_SR; // Status Register
AT91_REG SUPC_FWUTR; // Flash Wake-up Timer Register
} AT91S_SUPC, *AT91PS_SUPC;
#else
#define SUPC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SUPC_CR) Control Register
#define SUPC_BOMR (AT91_CAST(AT91_REG *) 0x00000004) // (SUPC_BOMR) Brown Out Mode Register
#define SUPC_MR (AT91_CAST(AT91_REG *) 0x00000008) // (SUPC_MR) Mode Register
#define SUPC_WUMR (AT91_CAST(AT91_REG *) 0x0000000C) // (SUPC_WUMR) Wake Up Mode Register
#define SUPC_WUIR (AT91_CAST(AT91_REG *) 0x00000010) // (SUPC_WUIR) Wake Up Inputs Register
#define SUPC_SR (AT91_CAST(AT91_REG *) 0x00000014) // (SUPC_SR) Status Register
#define SUPC_FWUTR (AT91_CAST(AT91_REG *) 0x00000018) // (SUPC_FWUTR) Flash Wake-up Timer Register
#endif
// -------- SUPC_CR : (SUPC Offset: 0x0) Control Register --------
#define AT91C_SUPC_SHDW (0x1 << 0) // (SUPC) Shut Down Command
#define AT91C_SUPC_SHDWEOF (0x1 << 1) // (SUPC) Shut Down after End Of Frame
#define AT91C_SUPC_VROFF (0x1 << 2) // (SUPC) Voltage Regulator Off
#define AT91C_SUPC_XTALSEL (0x1 << 3) // (SUPC) Crystal Oscillator Select
#define AT91C_SUPC_KEY (0xFF << 24) // (SUPC) Supply Controller Writing Protection Key
// -------- SUPC_BOMR : (SUPC Offset: 0x4) Brown Out Mode Register --------
#define AT91C_SUPC_BODTH (0xF << 0) // (SUPC) Brown Out Threshold
#define AT91C_SUPC_BODSMPL (0x7 << 8) // (SUPC) Brown Out Sampling Period
#define AT91C_SUPC_BODSMPL_DISABLED (0x0 << 8) // (SUPC) Brown Out Detector disabled
#define AT91C_SUPC_BODSMPL_CONTINUOUS (0x1 << 8) // (SUPC) Continuous Brown Out Detector
#define AT91C_SUPC_BODSMPL_32_SLCK (0x2 << 8) // (SUPC) Brown Out Detector enabled one SLCK period every 32 SLCK periods
#define AT91C_SUPC_BODSMPL_256_SLCK (0x3 << 8) // (SUPC) Brown Out Detector enabled one SLCK period every 256 SLCK periods
#define AT91C_SUPC_BODSMPL_2048_SLCK (0x4 << 8) // (SUPC) Brown Out Detector enabled one SLCK period every 2048 SLCK periods
#define AT91C_SUPC_BODRSTEN (0x1 << 12) // (SUPC) Brownout Reset Enable
// -------- SUPC_MR : (SUPC Offset: 0x8) Supply Controller Mode Register --------
#define AT91C_SUPC_LCDOUT (0xF << 0) // (SUPC) LCD Charge Pump Output Voltage Selection
#define AT91C_SUPC_LCDMODE (0x3 << 4) // (SUPC) Segment LCD Supply Mode
#define AT91C_SUPC_LCDMODE_OFF (0x0 << 4) // (SUPC) The internal and external supply sources are both deselected and the on-chip charge pump is turned off
#define AT91C_SUPC_LCDMODE_OFF_AFTER_EOF (0x1 << 4) // (SUPC) At the End Of Frame from LCD controller, the internal and external supply sources are both deselected and the on-chip charge pump is turned off
#define AT91C_SUPC_LCDMODE_EXTERNAL (0x2 << 4) // (SUPC) The external supply source is selected
#define AT91C_SUPC_LCDMODE_INTERNAL (0x3 << 4) // (SUPC) The internal supply source is selected and the on-chip charge pump is turned on
#define AT91C_SUPC_VRDEEP (0x1 << 8) // (SUPC) Voltage Regulator Deep Mode
#define AT91C_SUPC_VRVDD (0x7 << 9) // (SUPC) Voltage Regulator Output Voltage Selection
#define AT91C_SUPC_VRRSTEN (0x1 << 12) // (SUPC) Voltage Regulation Loss Reset Enable
#define AT91C_SUPC_SRAMON (0x1 << 17) // (SUPC) SRAM ON
#define AT91C_SUPC_RTCON (0x1 << 18) // (SUPC) Real Time Clock Power switch ON
#define AT91C_SUPC_FLASHON (0x1 << 19) // (SUPC) Flash Power switch On
#define AT91C_SUPC_BYPASS (0x1 << 20) // (SUPC) 32kHz oscillator bypass
#define AT91C_SUPC_MKEY (0xFF << 24) // (SUPC) Supply Controller Writing Protection Key
// -------- SUPC_WUMR : (SUPC Offset: 0xc) Wake Up Mode Register --------
#define AT91C_SUPC_FWUPEN (0x1 << 0) // (SUPC) Force Wake Up Enable
#define AT91C_SUPC_BODEN (0x1 << 1) // (SUPC) Brown Out Wake Up Enable
#define AT91C_SUPC_RTTEN (0x1 << 2) // (SUPC) Real Time Timer Wake Up Enable
#define AT91C_SUPC_RTCEN (0x1 << 3) // (SUPC) Real Time Clock Wake Up Enable
#define AT91C_SUPC_FWUPDBC (0x7 << 8) // (SUPC) Force Wake Up debouncer
#define AT91C_SUPC_FWUPDBC_IMMEDIATE (0x0 << 8) // (SUPC) Immediate, No debouncing, detected active at least one Slow clock edge
#define AT91C_SUPC_FWUPDBC_3_SLCK (0x1 << 8) // (SUPC) An enabled Wake Up input shall be low for at least 3 SLCK periods
#define AT91C_SUPC_FWUPDBC_32_SLCK (0x2 << 8) // (SUPC) An enabled Wake Up input shall be low for at least 32 SLCK periods
#define AT91C_SUPC_FWUPDBC_512_SLCK (0x3 << 8) // (SUPC) An enabled Wake Up input shall be low for at least 512 SLCK periods
#define AT91C_SUPC_FWUPDBC_4096_SLCK (0x4 << 8) // (SUPC) An enabled Wake Up input shall be low for at least 4096 SLCK periods
#define AT91C_SUPC_FWUPDBC_32768_SLCK (0x5 << 8) // (SUPC) An enabled Wake Up input shall be low for at least 32768 SLCK periods
#define AT91C_SUPC_WKUPDBC (0x7 << 12) // (SUPC) Force Wake Up debouncer
#define AT91C_SUPC_WKUPDBC_IMMEDIATE (0x0 << 12) // (SUPC) Immediate, No debouncing, detected active at least one Slow clock edge
#define AT91C_SUPC_WKUPDBC_3_SLCK (0x1 << 12) // (SUPC) FWUP shall be low for at least 3 SLCK periods
#define AT91C_SUPC_WKUPDBC_32_SLCK (0x2 << 12) // (SUPC) FWUP shall be low for at least 32 SLCK periods
#define AT91C_SUPC_WKUPDBC_512_SLCK (0x3 << 12) // (SUPC) FWUP shall be low for at least 512 SLCK periods
#define AT91C_SUPC_WKUPDBC_4096_SLCK (0x4 << 12) // (SUPC) FWUP shall be low for at least 4096 SLCK periods
#define AT91C_SUPC_WKUPDBC_32768_SLCK (0x5 << 12) // (SUPC) FWUP shall be low for at least 32768 SLCK periods
// -------- SUPC_WUIR : (SUPC Offset: 0x10) Wake Up Inputs Register --------
#define AT91C_SUPC_WKUPEN0 (0x1 << 0) // (SUPC) Wake Up Input Enable 0
#define AT91C_SUPC_WKUPEN1 (0x1 << 1) // (SUPC) Wake Up Input Enable 1
#define AT91C_SUPC_WKUPEN2 (0x1 << 2) // (SUPC) Wake Up Input Enable 2
#define AT91C_SUPC_WKUPEN3 (0x1 << 3) // (SUPC) Wake Up Input Enable 3
#define AT91C_SUPC_WKUPEN4 (0x1 << 4) // (SUPC) Wake Up Input Enable 4
#define AT91C_SUPC_WKUPEN5 (0x1 << 5) // (SUPC) Wake Up Input Enable 5
#define AT91C_SUPC_WKUPEN6 (0x1 << 6) // (SUPC) Wake Up Input Enable 6
#define AT91C_SUPC_WKUPEN7 (0x1 << 7) // (SUPC) Wake Up Input Enable 7
#define AT91C_SUPC_WKUPEN8 (0x1 << 8) // (SUPC) Wake Up Input Enable 8
#define AT91C_SUPC_WKUPEN9 (0x1 << 9) // (SUPC) Wake Up Input Enable 9
#define AT91C_SUPC_WKUPEN10 (0x1 << 10) // (SUPC) Wake Up Input Enable 10
#define AT91C_SUPC_WKUPEN11 (0x1 << 11) // (SUPC) Wake Up Input Enable 11
#define AT91C_SUPC_WKUPEN12 (0x1 << 12) // (SUPC) Wake Up Input Enable 12
#define AT91C_SUPC_WKUPEN13 (0x1 << 13) // (SUPC) Wake Up Input Enable 13
#define AT91C_SUPC_WKUPEN14 (0x1 << 14) // (SUPC) Wake Up Input Enable 14
#define AT91C_SUPC_WKUPEN15 (0x1 << 15) // (SUPC) Wake Up Input Enable 15
#define AT91C_SUPC_WKUPT0 (0x1 << 16) // (SUPC) Wake Up Input Transition 0
#define AT91C_SUPC_WKUPT1 (0x1 << 17) // (SUPC) Wake Up Input Transition 1
#define AT91C_SUPC_WKUPT2 (0x1 << 18) // (SUPC) Wake Up Input Transition 2
#define AT91C_SUPC_WKUPT3 (0x1 << 19) // (SUPC) Wake Up Input Transition 3
#define AT91C_SUPC_WKUPT4 (0x1 << 20) // (SUPC) Wake Up Input Transition 4
#define AT91C_SUPC_WKUPT5 (0x1 << 21) // (SUPC) Wake Up Input Transition 5
#define AT91C_SUPC_WKUPT6 (0x1 << 22) // (SUPC) Wake Up Input Transition 6
#define AT91C_SUPC_WKUPT7 (0x1 << 23) // (SUPC) Wake Up Input Transition 7
#define AT91C_SUPC_WKUPT8 (0x1 << 24) // (SUPC) Wake Up Input Transition 8
#define AT91C_SUPC_WKUPT9 (0x1 << 25) // (SUPC) Wake Up Input Transition 9
#define AT91C_SUPC_WKUPT10 (0x1 << 26) // (SUPC) Wake Up Input Transition 10
#define AT91C_SUPC_WKUPT11 (0x1 << 27) // (SUPC) Wake Up Input Transition 11
#define AT91C_SUPC_WKUPT12 (0x1 << 28) // (SUPC) Wake Up Input Transition 12
#define AT91C_SUPC_WKUPT13 (0x1 << 29) // (SUPC) Wake Up Input Transition 13
#define AT91C_SUPC_WKUPT14 (0x1 << 30) // (SUPC) Wake Up Input Transition 14
#define AT91C_SUPC_WKUPT15 (0x1 << 31) // (SUPC) Wake Up Input Transition 15
// -------- SUPC_SR : (SUPC Offset: 0x14) Status Register --------
#define AT91C_SUPC_FWUPS (0x1 << 0) // (SUPC) Force Wake Up Status
#define AT91C_SUPC_WKUPS (0x1 << 1) // (SUPC) Wake Up Status
#define AT91C_SUPC_BODWS (0x1 << 2) // (SUPC) BOD Detection Wake Up Status
#define AT91C_SUPC_VRRSTS (0x1 << 3) // (SUPC) Voltage regulation Loss Reset Status
#define AT91C_SUPC_BODRSTS (0x1 << 4) // (SUPC) BOD detection Reset Status
#define AT91C_SUPC_BODS (0x1 << 5) // (SUPC) BOD Status
#define AT91C_SUPC_BROWNOUT (0x1 << 6) // (SUPC) BOD Output Status
#define AT91C_SUPC_OSCSEL (0x1 << 7) // (SUPC) 32kHz Oscillator Selection Status
#define AT91C_SUPC_LCDS (0x1 << 8) // (SUPC) LCD Status
#define AT91C_SUPC_GPBRS (0x1 << 9) // (SUPC) General Purpose Back-up registers Status
#define AT91C_SUPC_RTS (0x1 << 10) // (SUPC) Clock Status
#define AT91C_SUPC_FLASHS (0x1 << 11) // (SUPC) FLASH Memory Status
#define AT91C_SUPC_WKUPIS0 (0x1 << 16) // (SUPC) WKUP Input 0 Status
#define AT91C_SUPC_WKUPIS1 (0x1 << 17) // (SUPC) WKUP Input 1 Status
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