📄 at91sam9m10.h
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#define AT91C_DDRC2_TXARD_7 (0x7) // (HDDRSDRC2) Value : 7
#define AT91C_DDRC2_TXARD_8 (0x8) // (HDDRSDRC2) Value : 8
#define AT91C_DDRC2_TXARD_9 (0x9) // (HDDRSDRC2) Value : 9
#define AT91C_DDRC2_TXARD_10 (0xA) // (HDDRSDRC2) Value : 10
#define AT91C_DDRC2_TXARD_11 (0xB) // (HDDRSDRC2) Value : 11
#define AT91C_DDRC2_TXARD_12 (0xC) // (HDDRSDRC2) Value : 12
#define AT91C_DDRC2_TXARD_13 (0xD) // (HDDRSDRC2) Value : 13
#define AT91C_DDRC2_TXARD_14 (0xE) // (HDDRSDRC2) Value : 14
#define AT91C_DDRC2_TXARD_15 (0xF) // (HDDRSDRC2) Value : 15
#define AT91C_DDRC2_TXARDS (0xF << 8) // (HDDRSDRC2) Exit active power down delay to read command in 'Slow Exit' mode.
#define AT91C_DDRC2_TXARDS_0 (0x0 << 8) // (HDDRSDRC2) Value : 0
#define AT91C_DDRC2_TXARDS_1 (0x1 << 8) // (HDDRSDRC2) Value : 1
#define AT91C_DDRC2_TXARDS_2 (0x2 << 8) // (HDDRSDRC2) Value : 2
#define AT91C_DDRC2_TXARDS_3 (0x3 << 8) // (HDDRSDRC2) Value : 3
#define AT91C_DDRC2_TXARDS_4 (0x4 << 8) // (HDDRSDRC2) Value : 4
#define AT91C_DDRC2_TXARDS_5 (0x5 << 8) // (HDDRSDRC2) Value : 5
#define AT91C_DDRC2_TXARDS_6 (0x6 << 8) // (HDDRSDRC2) Value : 6
#define AT91C_DDRC2_TXARDS_7 (0x7 << 8) // (HDDRSDRC2) Value : 7
#define AT91C_DDRC2_TXARDS_8 (0x8 << 8) // (HDDRSDRC2) Value : 8
#define AT91C_DDRC2_TXARDS_9 (0x9 << 8) // (HDDRSDRC2) Value : 9
#define AT91C_DDRC2_TXARDS_10 (0xA << 8) // (HDDRSDRC2) Value : 10
#define AT91C_DDRC2_TXARDS_11 (0xB << 8) // (HDDRSDRC2) Value : 11
#define AT91C_DDRC2_TXARDS_12 (0xC << 8) // (HDDRSDRC2) Value : 12
#define AT91C_DDRC2_TXARDS_13 (0xD << 8) // (HDDRSDRC2) Value : 13
#define AT91C_DDRC2_TXARDS_14 (0xE << 8) // (HDDRSDRC2) Value : 14
#define AT91C_DDRC2_TXARDS_15 (0xF << 8) // (HDDRSDRC2) Value : 15
#define AT91C_DDRC2_TRPA (0xF << 16) // (HDDRSDRC2) Row precharge all delay
#define AT91C_DDRC2_TRPA_0 (0x0 << 16) // (HDDRSDRC2) Value : 0
#define AT91C_DDRC2_TRPA_1 (0x1 << 16) // (HDDRSDRC2) Value : 1
#define AT91C_DDRC2_TRPA_2 (0x2 << 16) // (HDDRSDRC2) Value : 2
#define AT91C_DDRC2_TRPA_3 (0x3 << 16) // (HDDRSDRC2) Value : 3
#define AT91C_DDRC2_TRPA_4 (0x4 << 16) // (HDDRSDRC2) Value : 4
#define AT91C_DDRC2_TRPA_5 (0x5 << 16) // (HDDRSDRC2) Value : 5
#define AT91C_DDRC2_TRPA_6 (0x6 << 16) // (HDDRSDRC2) Value : 6
#define AT91C_DDRC2_TRPA_7 (0x7 << 16) // (HDDRSDRC2) Value : 7
#define AT91C_DDRC2_TRPA_8 (0x8 << 16) // (HDDRSDRC2) Value : 8
#define AT91C_DDRC2_TRPA_9 (0x9 << 16) // (HDDRSDRC2) Value : 9
#define AT91C_DDRC2_TRPA_10 (0xA << 16) // (HDDRSDRC2) Value : 10
#define AT91C_DDRC2_TRPA_11 (0xB << 16) // (HDDRSDRC2) Value : 11
#define AT91C_DDRC2_TRPA_12 (0xC << 16) // (HDDRSDRC2) Value : 12
#define AT91C_DDRC2_TRPA_13 (0xD << 16) // (HDDRSDRC2) Value : 13
#define AT91C_DDRC2_TRPA_14 (0xE << 16) // (HDDRSDRC2) Value : 14
#define AT91C_DDRC2_TRPA_15 (0xF << 16) // (HDDRSDRC2) Value : 15
#define AT91C_DDRC2_TRTP (0xF << 24) // (HDDRSDRC2) Read to Precharge delay
#define AT91C_DDRC2_TRTP_0 (0x0 << 24) // (HDDRSDRC2) Value : 0
#define AT91C_DDRC2_TRTP_1 (0x1 << 24) // (HDDRSDRC2) Value : 1
#define AT91C_DDRC2_TRTP_2 (0x2 << 24) // (HDDRSDRC2) Value : 2
#define AT91C_DDRC2_TRTP_3 (0x3 << 24) // (HDDRSDRC2) Value : 3
#define AT91C_DDRC2_TRTP_4 (0x4 << 24) // (HDDRSDRC2) Value : 4
#define AT91C_DDRC2_TRTP_5 (0x5 << 24) // (HDDRSDRC2) Value : 5
#define AT91C_DDRC2_TRTP_6 (0x6 << 24) // (HDDRSDRC2) Value : 6
#define AT91C_DDRC2_TRTP_7 (0x7 << 24) // (HDDRSDRC2) Value : 7
#define AT91C_DDRC2_TRTP_8 (0x8 << 24) // (HDDRSDRC2) Value : 8
#define AT91C_DDRC2_TRTP_9 (0x9 << 24) // (HDDRSDRC2) Value : 9
#define AT91C_DDRC2_TRTP_10 (0xA << 24) // (HDDRSDRC2) Value : 10
#define AT91C_DDRC2_TRTP_11 (0xB << 24) // (HDDRSDRC2) Value : 11
#define AT91C_DDRC2_TRTP_12 (0xC << 24) // (HDDRSDRC2) Value : 12
#define AT91C_DDRC2_TRTP_13 (0xD << 24) // (HDDRSDRC2) Value : 13
#define AT91C_DDRC2_TRTP_14 (0xE << 24) // (HDDRSDRC2) Value : 14
#define AT91C_DDRC2_TRTP_15 (0xF << 24) // (HDDRSDRC2) Value : 15
// -------- HDDRSDRC2_T3PR : (HDDRSDRC2 Offset: 0x18) Timing3 Register --------
#define AT91C_DDRC2_TANPD (0xF << 0) // (HDDRSDRC2) ODT to power down entry
#define AT91C_DDRC2_TANPD_0 (0x0) // (HDDRSDRC2) Value : 0
#define AT91C_DDRC2_TANPD_1 (0x1) // (HDDRSDRC2) Value : 1
#define AT91C_DDRC2_TANPD_2 (0x2) // (HDDRSDRC2) Value : 2
#define AT91C_DDRC2_TANPD_3 (0x3) // (HDDRSDRC2) Value : 3
#define AT91C_DDRC2_TANPD_4 (0x4) // (HDDRSDRC2) Value : 4
#define AT91C_DDRC2_TANPD_5 (0x5) // (HDDRSDRC2) Value : 5
#define AT91C_DDRC2_TANPD_6 (0x6) // (HDDRSDRC2) Value : 6
#define AT91C_DDRC2_TANPD_7 (0x7) // (HDDRSDRC2) Value : 7
#define AT91C_DDRC2_TANPD_8 (0x8) // (HDDRSDRC2) Value : 8
#define AT91C_DDRC2_TANPD_9 (0x9) // (HDDRSDRC2) Value : 9
#define AT91C_DDRC2_TANPD_10 (0xA) // (HDDRSDRC2) Value : 10
#define AT91C_DDRC2_TANPD_11 (0xB) // (HDDRSDRC2) Value : 11
#define AT91C_DDRC2_TANPD_12 (0xC) // (HDDRSDRC2) Value : 12
#define AT91C_DDRC2_TANPD_13 (0xD) // (HDDRSDRC2) Value : 13
#define AT91C_DDRC2_TANPD_14 (0xE) // (HDDRSDRC2) Value : 14
#define AT91C_DDRC2_TANPD_15 (0xF) // (HDDRSDRC2) Value : 15
#define AT91C_DDRC2_TAXPD (0xF << 4) // (HDDRSDRC2) ODT power down exit
#define AT91C_DDRC2_TAXPD_0 (0x0 << 4) // (HDDRSDRC2) Value : 0
#define AT91C_DDRC2_TAXPD_1 (0x1 << 4) // (HDDRSDRC2) Value : 1
#define AT91C_DDRC2_TAXPD_2 (0x2 << 4) // (HDDRSDRC2) Value : 2
#define AT91C_DDRC2_TAXPD_3 (0x3 << 4) // (HDDRSDRC2) Value : 3
#define AT91C_DDRC2_TAXPD_4 (0x4 << 4) // (HDDRSDRC2) Value : 4
#define AT91C_DDRC2_TAXPD_5 (0x5 << 4) // (HDDRSDRC2) Value : 5
#define AT91C_DDRC2_TAXPD_6 (0x6 << 4) // (HDDRSDRC2) Value : 6
#define AT91C_DDRC2_TAXPD_7 (0x7 << 4) // (HDDRSDRC2) Value : 7
#define AT91C_DDRC2_TAXPD_8 (0x8 << 4) // (HDDRSDRC2) Value : 8
#define AT91C_DDRC2_TAXPD_9 (0x9 << 4) // (HDDRSDRC2) Value : 9
#define AT91C_DDRC2_TAXPD_10 (0xA << 4) // (HDDRSDRC2) Value : 10
#define AT91C_DDRC2_TAXPD_11 (0xB << 4) // (HDDRSDRC2) Value : 11
#define AT91C_DDRC2_TAXPD_12 (0xC << 4) // (HDDRSDRC2) Value : 12
#define AT91C_DDRC2_TAXPD_13 (0xD << 4) // (HDDRSDRC2) Value : 13
#define AT91C_DDRC2_TAXPD_14 (0xE << 4) // (HDDRSDRC2) Value : 14
#define AT91C_DDRC2_TAXPD_15 (0xF << 4) // (HDDRSDRC2) Value : 15
#define AT91C_DDRC2_TAOFPD (0xF << 8) // (HDDRSDRC2) ODT turn off in power down mode
#define AT91C_DDRC2_TAOFPD_0 (0x0 << 8) // (HDDRSDRC2) Value : 0
#define AT91C_DDRC2_TAOFPD_1 (0x1 << 8) // (HDDRSDRC2) Value : 1
#define AT91C_DDRC2_TAOFPD_2 (0x2 << 8) // (HDDRSDRC2) Value : 2
#define AT91C_DDRC2_TAOFPD_3 (0x3 << 8) // (HDDRSDRC2) Value : 3
#define AT91C_DDRC2_TAOFPD_4 (0x4 << 8) // (HDDRSDRC2) Value : 4
#define AT91C_DDRC2_TAOFPD_5 (0x5 << 8) // (HDDRSDRC2) Value : 5
#define AT91C_DDRC2_TAOFPD_6 (0x6 << 8) // (HDDRSDRC2) Value : 6
#define AT91C_DDRC2_TAOFPD_7 (0x7 << 8) // (HDDRSDRC2) Value : 7
#define AT91C_DDRC2_TAOFPD_8 (0x8 << 8) // (HDDRSDRC2) Value : 8
#define AT91C_DDRC2_TAOFPD_9 (0x9 << 8) // (HDDRSDRC2) Value : 9
#define AT91C_DDRC2_TAOFPD_10 (0xA << 8) // (HDDRSDRC2) Value : 10
#define AT91C_DDRC2_TAOFPD_11 (0xB << 8) // (HDDRSDRC2) Value : 11
#define AT91C_DDRC2_TAOFPD_12 (0xC << 8) // (HDDRSDRC2) Value : 12
#define AT91C_DDRC2_TAOFPD_13 (0xD << 8) // (HDDRSDRC2) Value : 13
#define AT91C_DDRC2_TAOFPD_14 (0xE << 8) // (HDDRSDRC2) Value : 14
#define AT91C_DDRC2_TAOFPD_15 (0xF << 8) // (HDDRSDRC2) Value : 15
#define AT91C_DDRC2_TAOFD (0xF << 12) // (HDDRSDRC2) ODT turn off delay
#define AT91C_DDRC2_TAOFD_0 (0x0 << 12) // (HDDRSDRC2) Value : 0
#define AT91C_DDRC2_TAOFD_1 (0x1 << 12) // (HDDRSDRC2) Value : 1
#define AT91C_DDRC2_TAOFD_2 (0x2 << 12) // (HDDRSDRC2) Value : 2
#define AT91C_DDRC2_TAOFD_3 (0x3 << 12) // (HDDRSDRC2) Value : 3
#define AT91C_DDRC2_TAOFD_4 (0x4 << 12) // (HDDRSDRC2) Value : 4
#define AT91C_DDRC2_TAOFD_5 (0x5 << 12) // (HDDRSDRC2) Value : 5
#define AT91C_DDRC2_TAOFD_6 (0x6 << 12) // (HDDRSDRC2) Value : 6
#define AT91C_DDRC2_TAOFD_7 (0x7 << 12) // (HDDRSDRC2) Value : 7
#define AT91C_DDRC2_TAOFD_8 (0x8 << 12) // (HDDRSDRC2) Value : 8
#define AT91C_DDRC2_TAOFD_9 (0x9 << 12) // (HDDRSDRC2) Value : 9
#define AT91C_DDRC2_TAOFD_10 (0xA << 12) // (HDDRSDRC2) Value : 10
#define AT91C_DDRC2_TAOFD_11 (0xB << 12) // (HDDRSDRC2) Value : 11
#define AT91C_DDRC2_TAOFD_12 (0xC << 12) // (HDDRSDRC2) Value : 12
#define AT91C_DDRC2_TAOFD_13 (0xD << 12) // (HDDRSDRC2) Value : 13
#define AT91C_DDRC2_TAOFD_14 (0xE << 12) // (HDDRSDRC2) Value : 14
#define AT91C_DDRC2_TAOFD_15 (0xF << 12) // (HDDRSDRC2) Value : 15
#define AT91C_DDRC2_TAONPD (0xF << 16) // (HDDRSDRC2) ODT turn on in power down mode
#define AT91C_DDRC2_TAONPD_0 (0x0 << 16) // (HDDRSDRC2) Value : 0
#define AT91C_DDRC2_TAONPD_1 (0x1 << 16) // (HDDRSDRC2) Value : 1
#define AT91C_DDRC2_TAONPD_2 (0x2 << 16) // (HDDRSDRC2) Value : 2
#define AT91C_DDRC2_TAONPD_3 (0x3 << 16) // (HDDRSDRC2) Value : 3
#define AT91C_DDRC2_TAONPD_4 (0x4 << 16) // (HDDRSDRC2) Value : 4
#define AT91C_DDRC2_TAONPD_5 (0x5 << 16) // (HDDRSDRC2) Value : 5
#define AT91C_DDRC2_TAONPD_6 (0x6 << 16) // (HDDRSDRC2) Value : 6
#define AT91C_DDRC2_TAONPD_7 (0x7 << 16) // (HDDRSDRC2) Value : 7
#define AT91C_DDRC2_TAONPD_8 (0x8 << 16) // (HDDRSDRC2) Value : 8
#define AT91C_DDRC2_TAONPD_9 (0x9 << 16) // (HDDRSDRC2) Value : 9
#define AT91C_DDRC2_TAONPD_10 (0xA << 16) // (HDDRSDRC2) Value : 10
#define AT91C_DDRC2_TAONPD_11 (0xB << 16) // (HDDRSDRC2) Value : 11
#define AT91C_DDRC2_TAONPD_12 (0xC << 16) // (HDDRSDRC2) Value : 12
#define AT91C_DDRC2_TAONPD_13 (0xD << 16) // (HDDRSDRC2) Value : 13
#define AT91C_DDRC2_TAONPD_14 (0xE << 16) // (HDDRSDRC2) Value : 14
#define AT91C_DDRC2_TAONPD_15 (0xF << 16) // (HDDRSDRC2) Value : 15
// -------- HDDRSDRC2_LPR : (HDDRSDRC2 Offset: 0x1c) --------
#define AT91C_DDRC2_LPCB (0x3 << 0) // (HDDRSDRC2) Low-power Command Bit
#define AT91C_DDRC2_LPCB_DISABLED (0x0) // (HDDRSDRC2) Low-power Feature is inhibited: no power-down, self refresh and Deep power mode are issued to the SDRAM device.
#define AT91C_DDRC2_LPCB_SELFREFRESH (0x1) // (HDDRSDRC2) The DDRSDRAMC Controller issues a Self Refresh Command to the SDRAM device, the clock(s) is/are de-activated and the CKE signal is set low. The SDRAM device leaves the self refresh mode when accessed and enters it after the access.
#define AT91C_DDRC2_LPCB_POWERDOWN (0x2) // (HDDRSDRC2) The HDDRSDRC2 Controller issues a Power-down Command to the SDRAM device after each access, the CKE signal is set low. The SDRAM device leaves the power-down mode when accessed and enters it after the access.
#define AT91C_DDRC2_LPCB_DEEP_PWD (0x3) // (HDDRSDRC2) The HDDRSDRC2 Controller issues a Deep Power-down Command to the Mobile SDRAM device. This mode is unique to Mobile SDRAM devices
#define AT91C_DDRC2_CLK_FR (0x1 << 2) // (HDDRSDRC2) Clock frozen Command Bit
#define AT91C_DDRC2_CLK_FR_DISABLED (0x0 << 2) // (HDDRSDRC2) Low-power Feature is inhibited: no power-down, self refresh and Deep power mode are issued to the SDRAM device.
#define AT91C_DDRC2_CLK_FR_SELFREFRESH (0x1 << 2) // (HDDRSDRC2) The DDRSDRAMC Controller issues a Self Refresh Command to the SDRAM device, the clock(s) is/are de-activated and the CKE signal is set low. The SDRAM device leaves the self refresh mode when accessed and enters it after the access.
#define AT91C_DDRC2_CLK_FR_POWERDOWN (0x2 << 2) // (HDDRSDRC2) The HDDRSDRC2 Controller issues a Power-down Command to the SDRAM device after each access, the CKE signal is set low. The SDRAM device leaves the power-down mode when accessed and enters it after the access.
#define AT91C_DDRC2_CLK_FR_DEEP_PWD (0x3 << 2) // (HDDRSDRC2) The HDDRSDRC2 Controller issues a Deep Power-down Command to the Mobile SDRAM device. This mode is unique to Mobile SDRAM devices
#define AT91C_DDRC2_PASR (0x7 << 4) // (HDDRSDRC2) Partial Array Self Refresh
#define AT91C_ (0x0 << 8) // (HDDRSDRC2)
#define AT91C_DDRC2_DS (0x3 << 10) // (HDDRSDRC2) Drive strength
#define AT91C_DDRC2_TIMEOUT (0x3 << 12) // (HDDRSDRC2) low-power mode delay
#define AT91C_DDRC2_TIMEOUT_0 (0x0 << 12) // (HDDRSDRC2) The SDRAM controller activates the SDRAM low-power mode immediately after the end of the last transfer.
#define AT91C_DDRC2_TIMEOUT_64 (0x1 << 12) // (HDDRSDRC2) The SDRAM controller activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer.
#define AT91C_DDRC2_TIMEOUT_128 (0x2 << 12) // (HDDRSDRC2) The SDRAM controller activates the SDRAM low-power mode 128 clock cycles af⌨️ 快捷键说明
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