📄 at91sam9m10.h
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// -------- GPBR : (SYS Offset: 0x3d60) GPBR General Purpose Register --------
#define AT91C_GPBR_GPRV (0x0 << 0) // (SYS) General Purpose Register Value
// *****************************************************************************
// SOFTWARE API DEFINITION FOR External Bus Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_EBI {
AT91_REG EBI_DUMMY; // Dummy register - Do not use
} AT91S_EBI, *AT91PS_EBI;
#else
#define EBI_DUMMY (AT91_CAST(AT91_REG *) 0x00000000) // (EBI_DUMMY) Dummy register - Do not use
#endif
// *****************************************************************************
// SOFTWARE API DEFINITION FOR DDR2/SDRAM Controller
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_HDDRSDRC2 {
AT91_REG HDDRSDRC2_MR; // Mode Register
AT91_REG HDDRSDRC2_RTR; // Refresh Timer Register
AT91_REG HDDRSDRC2_CR; // Configuration Register
AT91_REG HDDRSDRC2_T0PR; // Timing0 Register
AT91_REG HDDRSDRC2_T1PR; // Timing1 Register
AT91_REG HDDRSDRC2_T2PR; // Timing2 Register
AT91_REG HDDRSDRC2_T3PR; // Timing3 Register
AT91_REG HDDRSDRC2_LPR; // Low-power Register
AT91_REG HDDRSDRC2_MDR; // Memory Device Register
AT91_REG HDDRSDRC2_DLL; // DLL Information Register
AT91_REG HDDRSDRC2_VER; // DLL Version Register
AT91_REG HDDRSDRC2_HS; // High Speed Register
AT91_REG HDDRSDRC2_DELAY1; // Pad delay1 Register
AT91_REG HDDRSDRC2_DELAY2; // Pad delay2 Register
AT91_REG HDDRSDRC2_DELAY3; // Pad delay3 Register
AT91_REG HDDRSDRC2_DELAY4; // Pad delay4 Register
AT91_REG HDDRSDRC2_DELAY5; // Pad delay5 Register
AT91_REG HDDRSDRC2_DELAY6; // Pad delay6 Register
AT91_REG HDDRSDRC2_DELAY7; // Pad delay7 Register
AT91_REG HDDRSDRC2_DELAY8; // Pad delay8 Register
AT91_REG Reserved0[37]; //
AT91_REG HDDRSDRC2_WPCR; // High Speed Register
AT91_REG HDDRSDRC2_WPSR; // High Speed Register
AT91_REG Reserved1[4]; //
AT91_REG HDDRSDRC2_VERSION; // Version Register
} AT91S_HDDRSDRC2, *AT91PS_HDDRSDRC2;
#else
#define HDDRSDRC2_MR (AT91_CAST(AT91_REG *) 0x00000000) // (HDDRSDRC2_MR) Mode Register
#define HDDRSDRC2_RTR (AT91_CAST(AT91_REG *) 0x00000004) // (HDDRSDRC2_RTR) Refresh Timer Register
#define HDDRSDRC2_CR (AT91_CAST(AT91_REG *) 0x00000008) // (HDDRSDRC2_CR) Configuration Register
#define HDDRSDRC2_T0PR (AT91_CAST(AT91_REG *) 0x0000000C) // (HDDRSDRC2_T0PR) Timing0 Register
#define HDDRSDRC2_T1PR (AT91_CAST(AT91_REG *) 0x00000010) // (HDDRSDRC2_T1PR) Timing1 Register
#define HDDRSDRC2_T2PR (AT91_CAST(AT91_REG *) 0x00000014) // (HDDRSDRC2_T2PR) Timing2 Register
#define HDDRSDRC2_T3PR (AT91_CAST(AT91_REG *) 0x00000018) // (HDDRSDRC2_T3PR) Timing3 Register
#define HDDRSDRC2_LPR (AT91_CAST(AT91_REG *) 0x0000001C) // (HDDRSDRC2_LPR) Low-power Register
#define HDDRSDRC2_MDR (AT91_CAST(AT91_REG *) 0x00000020) // (HDDRSDRC2_MDR) Memory Device Register
#define HDDRSDRC2_DLL (AT91_CAST(AT91_REG *) 0x00000024) // (HDDRSDRC2_DLL) DLL Information Register
#define HDDRSDRC2_DLL_VER (AT91_CAST(AT91_REG *) 0x00000028) // (HDDRSDRC2_DLL_VER) DLL Version Register
#define HDDRSDRC2_HS (AT91_CAST(AT91_REG *) 0x0000002C) // (HDDRSDRC2_HS) High Speed Register
#define HDDRSDRC2_DELAY1 (AT91_CAST(AT91_REG *) 0x00000030) // (HDDRSDRC2_DELAY1) Pad delay1 Register
#define HDDRSDRC2_DELAY2 (AT91_CAST(AT91_REG *) 0x00000034) // (HDDRSDRC2_DELAY2) Pad delay2 Register
#define HDDRSDRC2_DELAY3 (AT91_CAST(AT91_REG *) 0x00000038) // (HDDRSDRC2_DELAY3) Pad delay3 Register
#define HDDRSDRC2_DELAY4 (AT91_CAST(AT91_REG *) 0x0000003C) // (HDDRSDRC2_DELAY4) Pad delay4 Register
#define HDDRSDRC2_DELAY5 (AT91_CAST(AT91_REG *) 0x00000040) // (HDDRSDRC2_DELAY5) Pad delay5 Register
#define HDDRSDRC2_DELAY6 (AT91_CAST(AT91_REG *) 0x00000044) // (HDDRSDRC2_DELAY6) Pad delay6 Register
#define HDDRSDRC2_DELAY7 (AT91_CAST(AT91_REG *) 0x00000048) // (HDDRSDRC2_DELAY7) Pad delay7 Register
#define HDDRSDRC2_DELAY8 (AT91_CAST(AT91_REG *) 0x0000004C) // (HDDRSDRC2_DELAY8) Pad delay8 Register
#define HDDRSDRC2_WPCR (AT91_CAST(AT91_REG *) 0x000000E4) // (HDDRSDRC2_WPCR) High Speed Register
#define HDDRSDRC2_WPSR (AT91_CAST(AT91_REG *) 0x000000E8) // (HDDRSDRC2_WPSR) High Speed Register
#define HDDRSDRC2_VERSION (AT91_CAST(AT91_REG *) 0x000000FC) // (HDDRSDRC2_VERSION) Version Register
#endif
// -------- HDDRSDRC2_MR : (HDDRSDRC2 Offset: 0x0) Mode Register --------
#define AT91C_DDRC2_MODE (0x7 << 0) // (HDDRSDRC2) DDR/SDRAM Command Mode
#define AT91C_DDRC2_MODE_NORMAL_CMD (0x0) // (HDDRSDRC2) Normal Mode
#define AT91C_DDRC2_MODE_NOP_CMD (0x1) // (HDDRSDRC2) Issue a NOP Command at every access
#define AT91C_DDRC2_MODE_PRCGALL_CMD (0x2) // (HDDRSDRC2) Issue a All Banks Precharge Command at every access
#define AT91C_DDRC2_MODE_LMR_CMD (0x3) // (HDDRSDRC2) Issue a Load Mode Register at every access
#define AT91C_DDRC2_MODE_RFSH_CMD (0x4) // (HDDRSDRC2) Issue a Refresh
#define AT91C_DDRC2_MODE_EXT_LMR_CMD (0x5) // (HDDRSDRC2) Issue an Extended Load Mode Register
#define AT91C_DDRC2_MODE_DEEP_CMD (0x6) // (HDDRSDRC2) Enter Deep Power Mode
#define AT91C_DDRC2_MODE_Reserved (0x7) // (HDDRSDRC2) Reserved value
// -------- HDDRSDRC2_RTR : (HDDRSDRC2 Offset: 0x4) Refresh Timer Register --------
#define AT91C_DDRC2_COUNT (0xFFF << 0) // (HDDRSDRC2) Refresh Timer Count
// -------- HDDRSDRC2_CR : (HDDRSDRC2 Offset: 0x8) Configuration Register --------
#define AT91C_DDRC2_NC (0x3 << 0) // (HDDRSDRC2) Number of Column Bits
#define AT91C_DDRC2_NC_DDR9_SDR8 (0x0) // (HDDRSDRC2) DDR 9 Bits | SDR 8 Bits
#define AT91C_DDRC2_NC_DDR10_SDR9 (0x1) // (HDDRSDRC2) DDR 10 Bits | SDR 9 Bits
#define AT91C_DDRC2_NC_DDR11_SDR10 (0x2) // (HDDRSDRC2) DDR 11 Bits | SDR 10 Bits
#define AT91C_DDRC2_NC_DDR12_SDR11 (0x3) // (HDDRSDRC2) DDR 12 Bits | SDR 11 Bits
#define AT91C_DDRC2_NR (0x3 << 2) // (HDDRSDRC2) Number of Row Bits
#define AT91C_DDRC2_NR_11 (0x0 << 2) // (HDDRSDRC2) 11 Bits
#define AT91C_DDRC2_NR_12 (0x1 << 2) // (HDDRSDRC2) 12 Bits
#define AT91C_DDRC2_NR_13 (0x2 << 2) // (HDDRSDRC2) 13 Bits
#define AT91C_DDRC2_NR_14 (0x3 << 2) // (HDDRSDRC2) 14 Bits
#define AT91C_DDRC2_CAS (0x7 << 4) // (HDDRSDRC2) CAS Latency
#define AT91C_DDRC2_CAS_2 (0x2 << 4) // (HDDRSDRC2) 2 cycles (DDR1/SDR)
#define AT91C_DDRC2_CAS_3 (0x3 << 4) // (HDDRSDRC2) 3 cycles (DDR2/DDR1/SDR)
#define AT91C_DDRC2_CAS_4 (0x4 << 4) // (HDDRSDRC2) 4 cycles (DDR2)
#define AT91C_DDRC2_CAS_2_5 (0x6 << 4) // (HDDRSDRC2) 2.5 cycles (DDR1)
#define AT91C_DDRC2_DLL (0x1 << 7) // (HDDRSDRC2) DLL Reset
#define AT91C_DDRC2_DLL_RESET_DISABLED (0x0 << 7) // (HDDRSDRC2) DLL normal mode
#define AT91C_DDRC2_DLL_RESET_ENABLED (0x1 << 7) // (HDDRSDRC2) Reset DLL
#define AT91C_DDRC2_DIC_DS (0x1 << 8) // (HDDRSDRC2) Output driver impedance control
#define AT91C_DDRC2_OCD (0x7 << 12) // (HDDRSDRC2) Off chip driver
#define AT91C_DDRC2_OCD_EXIT (0x0 << 12) // (HDDRSDRC2) Exit OCD calibration mode.
#define AT91C_DDRC2_OCD_DEFAULT (0x7 << 12) // (HDDRSDRC2) Program OCD calibration default value.
#define AT91C_DDRC2_DQMS (0x1 << 16) // (HDDRSDRC2) Data Mask share
#define AT91C_DDRC2_DQMS_NOT_SHARED (0x0 << 16) // (HDDRSDRC2) Used DQM bits are not shared
#define AT91C_DDRC2_DQMS_SHARED (0x1 << 16) // (HDDRSDRC2) Used DQM bits are shared
#define AT91C_DDRC2_ENRDM (0x1 << 17) // (HDDRSDRC2) DQS/DATA phase error correction
#define AT91C_DDRC2_ENRDM_OFF (0x0 << 17) // (HDDRSDRC2) phase error correction disabled
#define AT91C_DDRC2_ENRDM_ON (0x1 << 17) // (HDDRSDRC2) phase error correction enabled
// -------- HDDRSDRC2_T0PR : (HDDRSDRC2 Offset: 0xc) Timing0 Register --------
#define AT91C_DDRC2_TRAS (0xF << 0) // (HDDRSDRC2) Active to precharge delay
#define AT91C_DDRC2_TRAS_0 (0x0) // (HDDRSDRC2) Value : 0
#define AT91C_DDRC2_TRAS_1 (0x1) // (HDDRSDRC2) Value : 1
#define AT91C_DDRC2_TRAS_2 (0x2) // (HDDRSDRC2) Value : 2
#define AT91C_DDRC2_TRAS_3 (0x3) // (HDDRSDRC2) Value : 3
#define AT91C_DDRC2_TRAS_4 (0x4) // (HDDRSDRC2) Value : 4
#define AT91C_DDRC2_TRAS_5 (0x5) // (HDDRSDRC2) Value : 5
#define AT91C_DDRC2_TRAS_6 (0x6) // (HDDRSDRC2) Value : 6
#define AT91C_DDRC2_TRAS_7 (0x7) // (HDDRSDRC2) Value : 7
#define AT91C_DDRC2_TRAS_8 (0x8) // (HDDRSDRC2) Value : 8
#define AT91C_DDRC2_TRAS_9 (0x9) // (HDDRSDRC2) Value : 9
#define AT91C_DDRC2_TRAS_10 (0xA) // (HDDRSDRC2) Value : 10
#define AT91C_DDRC2_TRAS_11 (0xB) // (HDDRSDRC2) Value : 11
#define AT91C_DDRC2_TRAS_12 (0xC) // (HDDRSDRC2) Value : 12
#define AT91C_DDRC2_TRAS_13 (0xD) // (HDDRSDRC2) Value : 13
#define AT91C_DDRC2_TRAS_14 (0xE) // (HDDRSDRC2) Value : 14
#define AT91C_DDRC2_TRAS_15 (0xF) // (HDDRSDRC2) Value : 15
#define AT91C_DDRC2_TRCD (0xF << 4) // (HDDRSDRC2) Row to column delay
#define AT91C_DDRC2_TRCD_0 (0x0 << 4) // (HDDRSDRC2) Value : 0
#define AT91C_DDRC2_TRCD_1 (0x1 << 4) // (HDDRSDRC2) Value : 1
#define AT91C_DDRC2_TRCD_2 (0x2 << 4) // (HDDRSDRC2) Value : 2
#define AT91C_DDRC2_TRCD_3 (0x3 << 4) // (HDDRSDRC2) Value : 3
#define AT91C_DDRC2_TRCD_4 (0x4 << 4) // (HDDRSDRC2) Value : 4
#define AT91C_DDRC2_TRCD_5 (0x5 << 4) // (HDDRSDRC2) Value : 5
#define AT91C_DDRC2_TRCD_6 (0x6 << 4) // (HDDRSDRC2) Value : 6
#define AT91C_DDRC2_TRCD_7 (0x7 << 4) // (HDDRSDRC2) Value : 7
#define AT91C_DDRC2_TRCD_8 (0x8 << 4) // (HDDRSDRC2) Value : 8
#define AT91C_DDRC2_TRCD_9 (0x9 << 4) // (HDDRSDRC2) Value : 9
#define AT91C_DDRC2_TRCD_10 (0xA << 4) // (HDDRSDRC2) Value : 10
#define AT91C_DDRC2_TRCD_11 (0xB << 4) // (HDDRSDRC2) Value : 11
#define AT91C_DDRC2_TRCD_12 (0xC << 4) // (HDDRSDRC2) Value : 12
#define AT91C_DDRC2_TRCD_13 (0xD << 4) // (HDDRSDRC2) Value : 13
#define AT91C_DDRC2_TRCD_14 (0xE << 4) // (HDDRSDRC2) Value : 14
#define AT91C_DDRC2_TRCD_15 (0xF << 4) // (HDDRSDRC2) Value : 15
#define AT91C_DDRC2_TWR (0xF << 8) // (HDDRSDRC2) Write recovery delay
#define AT91C_DDRC2_TWR_0 (0x0 << 8) // (HDDRSDRC2) Value : 0
#define AT91C_DDRC2_TWR_1 (0x1 << 8) // (HDDRSDRC2) Value : 1
#define AT91C_DDRC2_TWR_2 (0x2 << 8) // (HDDRSDRC2) Value : 2
#define AT91C_DDRC2_TWR_3 (0x3 << 8) // (HDDRSDRC2) Value : 3
#define AT91C_DDRC2_TWR_4 (0x4 << 8) // (HDDRSDRC2) Value : 4
#define AT91C_DDRC2_TWR_5 (0x5 << 8) // (HDDRSDRC2) Value : 5
#define AT91C_DDRC2_TWR_6 (0x6 << 8) // (HDDRSDRC2) Value : 6
#define AT91C_DDRC2_TWR_7 (0x7 << 8) // (HDDRSDRC2) Value : 7
#define AT91C_DDRC2_TWR_8 (0x8 << 8) // (HDDRSDRC2) Value : 8
#define AT91C_DDRC2_TWR_9 (0x9 << 8) // (HDDRSDRC2) Value : 9
#define AT91C_DDRC2_TWR_10 (0xA << 8) // (HDDRSDRC2) Value : 10
#define AT91C_DDRC2_TWR_11 (0xB << 8) // (HDDRSDRC2) Value : 11
#define AT91C_DDRC2_TWR_12 (0xC << 8) // (HDDRSDRC2) Value : 12
#define AT91C_DDRC2_TWR_13 (0xD << 8) // (HDDRSDRC2) Value : 13
#define AT91C_DDRC2_TWR_14 (0xE << 8) // (HDDRSDRC2) Value : 14
#define AT91C_DDRC2_TWR_15 (0xF << 8) // (HDDRSDRC2) Value : 15
#define AT91C_DDRC2_TRC (0xF << 12) // (HDDRSDRC2) Row cycle delay
#define AT91C_DDRC2_TRC_0 (0x0 << 12) // (HDDRSDRC2) Value : 0
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