📄 at91cap9.h
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#define AT91C_MATRIX_RCB3 (0x1 << 3) // (MATRIX) Remap Command Bit for LCD
#define AT91C_MATRIX_RCB4 (0x1 << 4) // (MATRIX) Remap Command Bit for 2DGC
#define AT91C_MATRIX_RCB5 (0x1 << 5) // (MATRIX) Remap Command Bit for ISI
#define AT91C_MATRIX_RCB6 (0x1 << 6) // (MATRIX) Remap Command Bit for DMA
#define AT91C_MATRIX_RCB7 (0x1 << 7) // (MATRIX) Remap Command Bit for EMAC
#define AT91C_MATRIX_RCB8 (0x1 << 8) // (MATRIX) Remap Command Bit for USB
#define AT91C_MATRIX_RCB9 (0x1 << 9) // (MATRIX) Remap Command Bit for USB
#define AT91C_MATRIX_RCB10 (0x1 << 10) // (MATRIX) Remap Command Bit for USB
#define AT91C_MATRIX_RCB11 (0x1 << 11) // (MATRIX) Remap Command Bit for USB
// *****************************************************************************
// SOFTWARE API DEFINITION FOR AHB CCFG Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_CCFG {
AT91_REG CCFG_RAM; // Slave 0 (Ram) Special Function Register
AT91_REG CCFG_MPBS0; // Slave 1 (MP Block Slave 0) Special Function Register
AT91_REG CCFG_UDPHS; // Slave 2 (AHB Periphs) Special Function Register
AT91_REG CCFG_MPBS1; // Slave 3 (MP Block Slave 1) Special Function Register
AT91_REG CCFG_EBICSA; // EBI Chip Select Assignement Register
AT91_REG CCFG_HDDRC2; // Slave 5 (DDRC Port 2) Special Function Register
AT91_REG CCFG_HDDRC3; // Slave 6 (DDRC Port 3) Special Function Register
AT91_REG CCFG_MPBS2; // Slave 7 (MP Block Slave 2) Special Function Register
AT91_REG CCFG_MPBS3; // Slave 7 (MP Block Slave 3) Special Function Register
AT91_REG CCFG_BRIDGE; // Slave 8 (APB Bridge) Special Function Register
AT91_REG Reserved0[49]; //
AT91_REG CCFG_MATRIXVERSION; // Version Register
} AT91S_CCFG, *AT91PS_CCFG;
#else
#define CCFG_RAM (AT91_CAST(AT91_REG *) 0x00000000) // (CCFG_RAM) Slave 0 (Ram) Special Function Register
#define CCFG_MPBS0 (AT91_CAST(AT91_REG *) 0x00000004) // (CCFG_MPBS0) Slave 1 (MP Block Slave 0) Special Function Register
#define CCFG_UDPHS (AT91_CAST(AT91_REG *) 0x00000008) // (CCFG_UDPHS) Slave 2 (AHB Periphs) Special Function Register
#define CCFG_MPBS1 (AT91_CAST(AT91_REG *) 0x0000000C) // (CCFG_MPBS1) Slave 3 (MP Block Slave 1) Special Function Register
#define CCFG_EBICSA (AT91_CAST(AT91_REG *) 0x00000010) // (CCFG_EBICSA) EBI Chip Select Assignement Register
#define CCFG_HDDRC2 (AT91_CAST(AT91_REG *) 0x00000014) // (CCFG_HDDRC2) Slave 5 (DDRC Port 2) Special Function Register
#define CCFG_HDDRC3 (AT91_CAST(AT91_REG *) 0x00000018) // (CCFG_HDDRC3) Slave 6 (DDRC Port 3) Special Function Register
#define CCFG_MPBS2 (AT91_CAST(AT91_REG *) 0x0000001C) // (CCFG_MPBS2) Slave 7 (MP Block Slave 2) Special Function Register
#define CCFG_MPBS3 (AT91_CAST(AT91_REG *) 0x00000020) // (CCFG_MPBS3) Slave 7 (MP Block Slave 3) Special Function Register
#define CCFG_BRIDGE (AT91_CAST(AT91_REG *) 0x00000024) // (CCFG_BRIDGE) Slave 8 (APB Bridge) Special Function Register
#define CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *) 0x000000EC) // (CCFG_MATRIXVERSION) Version Register
#endif
// -------- CCFG_UDPHS : (CCFG Offset: 0x8) UDPHS Configuration --------
#define AT91C_CCFG_UDPHS_UDP_SELECT (0x1 << 31) // (CCFG) UDPHS or UDP Selection
#define AT91C_CCFG_UDPHS_UDP_SELECT_UDPHS (0x0 << 31) // (CCFG) UDPHS Selected.
#define AT91C_CCFG_UDPHS_UDP_SELECT_UDP (0x1 << 31) // (CCFG) UDP Selected.
// -------- CCFG_EBICSA : (CCFG Offset: 0x10) EBI Chip Select Assignement Register --------
#define AT91C_EBI_CS1A (0x1 << 1) // (CCFG) Chip Select 1 Assignment
#define AT91C_EBI_CS1A_SMC (0x0 << 1) // (CCFG) Chip Select 1 is assigned to the Static Memory Controller.
#define AT91C_EBI_CS1A_BCRAMC (0x1 << 1) // (CCFG) Chip Select 1 is assigned to the BCRAM Controller.
#define AT91C_EBI_CS3A (0x1 << 3) // (CCFG) Chip Select 3 Assignment
#define AT91C_EBI_CS3A_SMC (0x0 << 3) // (CCFG) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.
#define AT91C_EBI_CS3A_SM (0x1 << 3) // (CCFG) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
#define AT91C_EBI_CS4A (0x1 << 4) // (CCFG) Chip Select 4 Assignment
#define AT91C_EBI_CS4A_SMC (0x0 << 4) // (CCFG) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.
#define AT91C_EBI_CS4A_CF (0x1 << 4) // (CCFG) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
#define AT91C_EBI_CS5A (0x1 << 5) // (CCFG) Chip Select 5 Assignment
#define AT91C_EBI_CS5A_SMC (0x0 << 5) // (CCFG) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC
#define AT91C_EBI_CS5A_CF (0x1 << 5) // (CCFG) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
#define AT91C_EBI_DBPUC (0x1 << 8) // (CCFG) Data Bus Pull-up Configuration
#define AT91C_EBI_DDRPUC (0x1 << 9) // (CCFG) DDDR DQS Pull-up Configuration
#define AT91C_EBI_SUP (0x1 << 16) // (CCFG) EBI Supply
#define AT91C_EBI_SUP_1V8 (0x0 << 16) // (CCFG) EBI Supply is 1.8V
#define AT91C_EBI_SUP_3V3 (0x1 << 16) // (CCFG) EBI Supply is 3.3V
#define AT91C_EBI_LP (0x1 << 17) // (CCFG) EBI Low Power Reduction
#define AT91C_EBI_LP_STD_DRIVE (0x0 << 17) // (CCFG) EBI Pads are in Standard drive
#define AT91C_EBI_LP_LOW_DRIVE (0x1 << 17) // (CCFG) EBI Pads are in Low Drive (Low Power)
#define AT91C_CCFG_DDR_SDR_SELECT (0x1 << 31) // (CCFG) DDR or SDR Selection
#define AT91C_CCFG_DDR_SDR_SELECT_DDR (0x0 << 31) // (CCFG) DDR Selected.
#define AT91C_CCFG_DDR_SDR_SELECT_SDR (0x1 << 31) // (CCFG) SDR Selected.
// -------- CCFG_BRIDGE : (CCFG Offset: 0x24) BRIDGE Configuration --------
#define AT91C_CCFG_AES_TDES_SELECT (0x1 << 31) // (CCFG) AES or TDES Selection
#define AT91C_CCFG_AES_TDES_SELECT_AES (0x0 << 31) // (CCFG) AES Selected.
#define AT91C_CCFG_AES_TDES_SELECT_TDES (0x1 << 31) // (CCFG) TDES Selected.
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_PDC {
AT91_REG PDC_RPR; // Receive Pointer Register
AT91_REG PDC_RCR; // Receive Counter Register
AT91_REG PDC_TPR; // Transmit Pointer Register
AT91_REG PDC_TCR; // Transmit Counter Register
AT91_REG PDC_RNPR; // Receive Next Pointer Register
AT91_REG PDC_RNCR; // Receive Next Counter Register
AT91_REG PDC_TNPR; // Transmit Next Pointer Register
AT91_REG PDC_TNCR; // Transmit Next Counter Register
AT91_REG PDC_PTCR; // PDC Transfer Control Register
AT91_REG PDC_PTSR; // PDC Transfer Status Register
} AT91S_PDC, *AT91PS_PDC;
#else
#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register
#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register
#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register
#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register
#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register
#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register
#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register
#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register
#endif
// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Debug Unit
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_DBGU {
AT91_REG DBGU_CR; // Control Register
AT91_REG DBGU_MR; // Mode Register
AT91_REG DBGU_IER; // Interrupt Enable Register
AT91_REG DBGU_IDR; // Interrupt Disable Register
AT91_REG DBGU_IMR; // Interrupt Mask Register
AT91_REG DBGU_CSR; // Channel Status Register
AT91_REG DBGU_RHR; // Receiver Holding Register
AT91_REG DBGU_THR; // Transmitter Holding Register
AT91_REG DBGU_BRGR; // Baud Rate Generator Register
AT91_REG Reserved0[7]; //
AT91_REG DBGU_CIDR; // Chip ID Register
AT91_REG DBGU_EXID; // Chip ID Extension Register
AT91_REG DBGU_FNTR; // Force NTRST Register
AT91_REG Reserved1[45]; //
AT91_REG DBGU_RPR; // Receive Pointer Register
AT91_REG DBGU_RCR; // Receive Counter Register
AT91_REG DBGU_TPR; // Transmit Pointer Register
AT91_REG DBGU_TCR; // Transmit Counter Register
AT91_REG DBGU_RNPR; // Receive Next Pointer Register
AT91_REG DBGU_RNCR; // Receive Next Counter Register
AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
AT91_REG DBGU_TNCR; // Transmit Next Counter Register
AT91_REG DBGU_PTCR; // PDC Transfer Control Register
AT91_REG DBGU_PTSR; // PDC Transfer Status Register
} AT91S_DBGU, *AT91PS_DBGU;
#else
#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register
#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register
#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register
#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register
#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register
#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register
#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register
#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register
#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register
#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register
#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register
#endif
// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver
#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter
#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits
// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
#define AT91C_US_TXRDY ⌨️ 快捷键说明
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