dds.hier_info

多功能函数发生器

raw_tck => ram_rom_data_reg[5].CLK
raw_tck => ram_rom_data_reg[4].CLK
raw_tck => ram_rom_data_reg[3].CLK
raw_tck => ram_rom_data_reg[2].CLK
raw_tck => ram_rom_data_reg[1].CLK
raw_tck => ram_rom_data_reg[0].CLK
raw_tck => ram_rom_data_shift_cntr_reg[3].CLK
raw_tck => ram_rom_data_shift_cntr_reg[2].CLK
raw_tck => ram_rom_data_shift_cntr_reg[1].CLK
raw_tck => ram_rom_data_shift_cntr_reg[0].CLK
raw_tck => ir_loaded_address_reg[3].CLK
raw_tck => ir_loaded_address_reg[2].CLK
raw_tck => ir_loaded_address_reg[1].CLK
raw_tck => ir_loaded_address_reg[0].CLK
raw_tck => bypass_reg_out.CLK
raw_tck => is_in_use_reg.CLK
raw_tck => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.TCK
raw_tck => ram_rom_addr_reg[7].CLK
raw_tck => tck_usr.DATAIN
tdi => ram_rom_addr_reg~8.DATAB
tdi => ram_rom_data_reg~0.DATAB
tdi => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.TDI
tdi => bypass_reg_out.DATAIN
usr1 => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.USR1
usr1 => dr_scan.IN0
usr1 => name_gen~0.IN0
jtag_state_cdr => name_gen~1.IN1
jtag_state_sdr => sdr.IN0
jtag_state_sdr => name_gen~1.IN0
jtag_state_sdr => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.SHIFT
jtag_state_e1dr => e1dr.IN1
jtag_state_udr => udr.IN0
jtag_state_udr => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.UPDATE
jtag_state_uir => ~NO_FANOUT~
clrn => bypass_reg_out.ACLR
clrn => is_in_use_reg.ACLR
ena => dr_scan.IN1
ena => name_gen~0.IN1
ena => bypass_reg_out.ENA
ir_in[0] => ram_rom_addr_reg[6].ACLR
ir_in[0] => ram_rom_addr_reg[5].ACLR
ir_in[0] => ram_rom_addr_reg[4].ACLR
ir_in[0] => ram_rom_addr_reg[3].ACLR
ir_in[0] => ram_rom_addr_reg[2].ACLR
ir_in[0] => ram_rom_addr_reg[1].ACLR
ir_in[0] => ram_rom_addr_reg[0].ACLR
ir_in[0] => ir_loaded_address_reg[3].ACLR
ir_in[0] => ir_loaded_address_reg[2].ACLR
ir_in[0] => ir_loaded_address_reg[1].ACLR
ir_in[0] => ir_loaded_address_reg[0].ACLR
ir_in[0] => tdo~1.OUTPUTSELECT
ir_in[0] => is_in_use_reg~1.OUTPUTSELECT
ir_in[0] => ram_rom_addr_reg[7].ACLR
ir_in[1] => process1~0.IN0
ir_in[1] => process1~2.IN1
ir_in[1] => ram_rom_incr_addr~0.IN0
ir_in[2] => process1~2.IN0
ir_in[2] => ram_rom_incr_addr~1.IN0
ir_in[2] => enable_write~0.IN0
ir_in[3] => process0~0.IN1
ir_in[3] => process1~1.IN0
ir_in[3] => ram_rom_data_shift_cntr_reg[2].ACLR
ir_in[3] => ram_rom_data_shift_cntr_reg[1].ACLR
ir_in[3] => ram_rom_data_shift_cntr_reg[0].ACLR
ir_in[3] => process4~0.IN1
ir_in[3] => ram_rom_data_shift_cntr_reg[3].ACLR
ir_in[4] => is_in_use_reg~0.OUTPUTSELECT
ir_out[0] <= is_in_use_reg.DB_MAX_OUTPUT_PORT_TYPE
ir_out[1] <= ir_loaded_address_reg[0].DB_MAX_OUTPUT_PORT_TYPE
ir_out[2] <= ir_loaded_address_reg[1].DB_MAX_OUTPUT_PORT_TYPE
ir_out[3] <= ir_loaded_address_reg[2].DB_MAX_OUTPUT_PORT_TYPE
ir_out[4] <= ir_loaded_address_reg[3].DB_MAX_OUTPUT_PORT_TYPE
irq <= <GND>
tdo <= tdo~1.DB_MAX_OUTPUT_PORT_TYPE


|dds|data_juchi:u33|altsyncram:altsyncram_component|altsyncram_7vt:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
ROM_DATA[0] => Mux~3.IN131
ROM_DATA[1] => Mux~2.IN131
ROM_DATA[2] => Mux~1.IN131
ROM_DATA[3] => Mux~0.IN131
ROM_DATA[4] => Mux~3.IN127
ROM_DATA[5] => Mux~2.IN127
ROM_DATA[6] => Mux~1.IN127
ROM_DATA[7] => Mux~0.IN127
ROM_DATA[8] => Mux~3.IN123
ROM_DATA[9] => Mux~2.IN123
ROM_DATA[10] => Mux~1.IN123
ROM_DATA[11] => Mux~0.IN123
ROM_DATA[12] => Mux~3.IN119
ROM_DATA[13] => Mux~2.IN119
ROM_DATA[14] => Mux~1.IN119
ROM_DATA[15] => Mux~0.IN119
ROM_DATA[16] => Mux~3.IN115
ROM_DATA[17] => Mux~2.IN115
ROM_DATA[18] => Mux~1.IN115
ROM_DATA[19] => Mux~0.IN115
ROM_DATA[20] => Mux~3.IN111
ROM_DATA[21] => Mux~2.IN111
ROM_DATA[22] => Mux~1.IN111
ROM_DATA[23] => Mux~0.IN111
ROM_DATA[24] => Mux~3.IN107
ROM_DATA[25] => Mux~2.IN107
ROM_DATA[26] => Mux~1.IN107
ROM_DATA[27] => Mux~0.IN107
ROM_DATA[28] => Mux~3.IN103
ROM_DATA[29] => Mux~2.IN103
ROM_DATA[30] => Mux~1.IN103
ROM_DATA[31] => Mux~0.IN103
ROM_DATA[32] => Mux~3.IN99
ROM_DATA[33] => Mux~2.IN99
ROM_DATA[34] => Mux~1.IN99
ROM_DATA[35] => Mux~0.IN99
ROM_DATA[36] => Mux~3.IN95
ROM_DATA[37] => Mux~2.IN95
ROM_DATA[38] => Mux~1.IN95
ROM_DATA[39] => Mux~0.IN95
ROM_DATA[40] => Mux~3.IN91
ROM_DATA[41] => Mux~2.IN91
ROM_DATA[42] => Mux~1.IN91
ROM_DATA[43] => Mux~0.IN91
ROM_DATA[44] => Mux~3.IN87
ROM_DATA[45] => Mux~2.IN87
ROM_DATA[46] => Mux~1.IN87
ROM_DATA[47] => Mux~0.IN87
ROM_DATA[48] => Mux~3.IN83
ROM_DATA[49] => Mux~2.IN83
ROM_DATA[50] => Mux~1.IN83
ROM_DATA[51] => Mux~0.IN83
ROM_DATA[52] => Mux~3.IN79
ROM_DATA[53] => Mux~2.IN79
ROM_DATA[54] => Mux~1.IN79
ROM_DATA[55] => Mux~0.IN79
ROM_DATA[56] => Mux~3.IN75
ROM_DATA[57] => Mux~2.IN75
ROM_DATA[58] => Mux~1.IN75
ROM_DATA[59] => Mux~0.IN75
ROM_DATA[60] => Mux~3.IN71
ROM_DATA[61] => Mux~2.IN71
ROM_DATA[62] => Mux~1.IN71
ROM_DATA[63] => Mux~0.IN71
ROM_DATA[64] => Mux~3.IN67
ROM_DATA[65] => Mux~2.IN67
ROM_DATA[66] => Mux~1.IN67
ROM_DATA[67] => Mux~0.IN67
ROM_DATA[68] => Mux~3.IN63
ROM_DATA[69] => Mux~2.IN63
ROM_DATA[70] => Mux~1.IN63
ROM_DATA[71] => Mux~0.IN63
ROM_DATA[72] => Mux~3.IN59
ROM_DATA[73] => Mux~2.IN59
ROM_DATA[74] => Mux~1.IN59
ROM_DATA[75] => Mux~0.IN59
ROM_DATA[76] => Mux~3.IN55
ROM_DATA[77] => Mux~2.IN55
ROM_DATA[78] => Mux~1.IN55
ROM_DATA[79] => Mux~0.IN55
TCK => word_counter[3].CLK
TCK => word_counter[2].CLK
TCK => word_counter[1].CLK
TCK => word_counter[0].CLK
TCK => WORD_SR[3].CLK
TCK => WORD_SR[2].CLK
TCK => WORD_SR[1].CLK
TCK => WORD_SR[0].CLK
TCK => word_counter[4].CLK
SHIFT => WORD_SR~0.OUTPUTSELECT
SHIFT => WORD_SR~1.OUTPUTSELECT
SHIFT => WORD_SR~2.OUTPUTSELECT
SHIFT => WORD_SR~3.OUTPUTSELECT
UPDATE => clear_signal.IN0
USR1 => clear_signal.IN1
ENA => WORD_SR[3].ENA
ENA => WORD_SR[2].ENA
ENA => WORD_SR[1].ENA
ENA => WORD_SR[0].ENA
TDI => WORD_SR~0.DATAA
TDO <= WORD_SR[0].DB_MAX_OUTPUT_PORT_TYPE


|dds|data_sin:u34
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
inclock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]


|dds|data_sin:u34|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_rot:auto_generated.address_a[0]
address_a[1] => altsyncram_rot:auto_generated.address_a[1]
address_a[2] => altsyncram_rot:auto_generated.address_a[2]
address_a[3] => altsyncram_rot:auto_generated.address_a[3]
address_a[4] => altsyncram_rot:auto_generated.address_a[4]
address_a[5] => altsyncram_rot:auto_generated.address_a[5]
address_a[6] => altsyncram_rot:auto_generated.address_a[6]
address_a[7] => altsyncram_rot:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_rot:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_rot:auto_generated.q_a[0]
q_a[1] <= altsyncram_rot:auto_generated.q_a[1]
q_a[2] <= altsyncram_rot:auto_generated.q_a[2]
q_a[3] <= altsyncram_rot:auto_generated.q_a[3]
q_a[4] <= altsyncram_rot:auto_generated.q_a[4]
q_a[5] <= altsyncram_rot:auto_generated.q_a[5]
q_a[6] <= altsyncram_rot:auto_generated.q_a[6]
q_a[7] <= altsyncram_rot:auto_generated.q_a[7]
q_b[0] <= <GND>


|dds|data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated
address_a[0] => altsyncram_6hb2:altsyncram1.address_a[0]
address_a[1] => altsyncram_6hb2:altsyncram1.address_a[1]
address_a[2] => altsyncram_6hb2:altsyncram1.address_a[2]
address_a[3] => altsyncram_6hb2:altsyncram1.address_a[3]
address_a[4] => altsyncram_6hb2:altsyncram1.address_a[4]
address_a[5] => altsyncram_6hb2:altsyncram1.address_a[5]
address_a[6] => altsyncram_6hb2:altsyncram1.address_a[6]
address_a[7] => altsyncram_6hb2:altsyncram1.address_a[7]
clock0 => altsyncram_6hb2:altsyncram1.clock0
q_a[0] <= altsyncram_6hb2:altsyncram1.q_a[0]
q_a[1] <= altsyncram_6hb2:altsyncram1.q_a[1]
q_a[2] <= altsyncram_6hb2:altsyncram1.q_a[2]
q_a[3] <= altsyncram_6hb2:altsyncram1.q_a[3]
q_a[4] <= altsyncram_6hb2:altsyncram1.q_a[4]
q_a[5] <= altsyncram_6hb2:altsyncram1.q_a[5]
q_a[6] <= altsyncram_6hb2:altsyncram1.q_a[6]
q_a[7] <= altsyncram_6hb2:altsyncram1.q_a[7]


|dds|data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|altsyncram_6hb2:altsyncram1
address_a[0] => ram_block3a0.PORTAADDR
address_a[0] => ram_block3a1.PORTAADDR
address_a[0] => ram_block3a2.PORTAADDR
address_a[0] => ram_block3a3.PORTAADDR
address_a[0] => ram_block3a4.PORTAADDR
address_a[0] => ram_block3a5.PORTAADDR
address_a[0] => ram_block3a6.PORTAADDR
address_a[0] => ram_block3a7.PORTAADDR
address_a[1] => ram_block3a0.PORTAADDR1
address_a[1] => ram_block3a1.PORTAADDR1
address_a[1] => ram_block3a2.PORTAADDR1
address_a[1] => ram_block3a3.PORTAADDR1
address_a[1] => ram_block3a4.PORTAADDR1
address_a[1] => ram_block3a5.PORTAADDR1
address_a[1] => ram_block3a6.PORTAADDR1
address_a[1] => ram_block3a7.PORTAADDR1
address_a[2] => ram_block3a0.PORTAADDR2
address_a[2] => ram_block3a1.PORTAADDR2
address_a[2] => ram_block3a2.PORTAADDR2
address_a[2] => ram_block3a3.PORTAADDR2
address_a[2] => ram_block3a4.PORTAADDR2
address_a[2] => ram_block3a5.PORTAADDR2
address_a[2] => ram_block3a6.PORTAADDR2
address_a[2] => ram_block3a7.PORTAADDR2
address_a[3] => ram_block3a0.PORTAADDR3
address_a[3] => ram_block3a1.PORTAADDR3
address_a[3] => ram_block3a2.PORTAADDR3
address_a[3] => ram_block3a3.PORTAADDR3
address_a[3] => ram_block3a4.PORTAADDR3
address_a[3] => ram_block3a5.PORTAADDR3
address_a[3] => ram_block3a6.PORTAADDR3
address_a[3] => ram_block3a7.PORTAADDR3
address_a[4] => ram_block3a0.PORTAADDR4
address_a[4] => ram_block3a1.PORTAADDR4
address_a[4] => ram_block3a2.PORTAADDR4
address_a[4] => ram_block3a3.PORTAADDR4
address_a[4] => ram_block3a4.PORTAADDR4
address_a[4] => ram_block3a5.PORTAADDR4
address_a[4] => ram_block3a6.PORTAADDR4
address_a[4] => ram_block3a7.PORTAADDR4
address_a[5] => ram_block3a0.PORTAADDR5
address_a[5] => ram_block3a1.PORTAADDR5
address_a[5] => ram_block3a2.PORTAADDR5
address_a[5] => ram_block3a3.PORTAADDR5
address_a[5] => ram_block3a4.PORTAADDR5
address_a[5] => ram_block3a5.PORTAADDR5
address_a[5] => ram_block3a6.PORTAADDR5
address_a[5] => ram_block3a7.PORTAADDR5
address_a[6] => ram_block3a0.PORTAADDR6
address_a[6] => ram_block3a1.PORTAADDR6
address_a[6] => ram_block3a2.PORTAADDR6
address_a[6] => ram_block3a3.PORTAADDR6
address_a[6] => ram_block3a4.PORTAADDR6
address_a[6] => ram_block3a5.PORTAADDR6
address_a[6] => ram_block3a6.PORTAADDR6
address_a[6] => ram_block3a7.PORTAADDR6
address_a[7] => ram_block3a0.PORTAADDR7
address_a[7] => ram_block3a1.PORTAADDR7
address_a[7] => ram_block3a2.PORTAADDR7
address_a[7] => ram_block3a3.PORTAADDR7
address_a[7] => ram_block3a4.PORTAADDR7
address_a[7] => ram_block3a5.PORTAADDR7
address_a[7] => ram_block3a6.PORTAADDR7
address_a[7] => ram_block3a7.PORTAADDR7
address_b[0] => ram_block3a0.PORTBADDR
address_b[0] => ram_block3a1.PORTBADDR
address_b[0] => ram_block3a2.PORTBADDR
address_b[0] => ram_block3a3.PORTBADDR
address_b[0] => ram_block3a4.PORTBADDR
address_b[0] => ram_block3a5.PORTBADDR
address_b[0] => ram_block3a6.PORTBADDR
address_b[0] => ram_block3a7.PORTBADDR
address_b[1] => ram_block3a0.PORTBADDR1
address_b[1] => ram_block3a1.PORTBADDR1
address_b[1] => ram_block3a2.PORTBADDR1
address_b[1] => ram_block3a3.PORTBADDR1
address_b[1] => ram_block3a4.PORTBADDR1
address_b[1] => ram_block3a5.PORTBADDR1
address_b[1] => ram_block3a6.PORTBADDR1
address_b[1] => ram_block3a7.PORTBADDR1
address_b[2] => ram_block3a0.PORTBADDR2
address_b[2] => ram_block3a1.PORTBADDR2
address_b[2] => ram_block3a2.PORTBADDR2
address_b[2] => ram_block3a3.PORTBADDR2
address_b[2] => ram_block3a4.PORTBADDR2
address_b[2] => ram_block3a5.PORTBADDR2
address_b[2]