dds.hier_info

多功能函数发生器

ROM_DATA[50] => Mux~1.IN83
ROM_DATA[51] => Mux~0.IN83
ROM_DATA[52] => Mux~3.IN79
ROM_DATA[53] => Mux~2.IN79
ROM_DATA[54] => Mux~1.IN79
ROM_DATA[55] => Mux~0.IN79
ROM_DATA[56] => Mux~3.IN75
ROM_DATA[57] => Mux~2.IN75
ROM_DATA[58] => Mux~1.IN75
ROM_DATA[59] => Mux~0.IN75
ROM_DATA[60] => Mux~3.IN71
ROM_DATA[61] => Mux~2.IN71
ROM_DATA[62] => Mux~1.IN71
ROM_DATA[63] => Mux~0.IN71
ROM_DATA[64] => Mux~3.IN67
ROM_DATA[65] => Mux~2.IN67
ROM_DATA[66] => Mux~1.IN67
ROM_DATA[67] => Mux~0.IN67
ROM_DATA[68] => Mux~3.IN63
ROM_DATA[69] => Mux~2.IN63
ROM_DATA[70] => Mux~1.IN63
ROM_DATA[71] => Mux~0.IN63
ROM_DATA[72] => Mux~3.IN59
ROM_DATA[73] => Mux~2.IN59
ROM_DATA[74] => Mux~1.IN59
ROM_DATA[75] => Mux~0.IN59
ROM_DATA[76] => Mux~3.IN55
ROM_DATA[77] => Mux~2.IN55
ROM_DATA[78] => Mux~1.IN55
ROM_DATA[79] => Mux~0.IN55
TCK => word_counter[3].CLK
TCK => word_counter[2].CLK
TCK => word_counter[1].CLK
TCK => word_counter[0].CLK
TCK => WORD_SR[3].CLK
TCK => WORD_SR[2].CLK
TCK => WORD_SR[1].CLK
TCK => WORD_SR[0].CLK
TCK => word_counter[4].CLK
SHIFT => WORD_SR~0.OUTPUTSELECT
SHIFT => WORD_SR~1.OUTPUTSELECT
SHIFT => WORD_SR~2.OUTPUTSELECT
SHIFT => WORD_SR~3.OUTPUTSELECT
UPDATE => clear_signal.IN0
USR1 => clear_signal.IN1
ENA => WORD_SR[3].ENA
ENA => WORD_SR[2].ENA
ENA => WORD_SR[1].ENA
ENA => WORD_SR[0].ENA
TDI => WORD_SR~0.DATAA
TDO <= WORD_SR[0].DB_MAX_OUTPUT_PORT_TYPE


|dds|data_juchi:u33
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
inclock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]


|dds|data_juchi:u33|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_7vt:auto_generated.address_a[0]
address_a[1] => altsyncram_7vt:auto_generated.address_a[1]
address_a[2] => altsyncram_7vt:auto_generated.address_a[2]
address_a[3] => altsyncram_7vt:auto_generated.address_a[3]
address_a[4] => altsyncram_7vt:auto_generated.address_a[4]
address_a[5] => altsyncram_7vt:auto_generated.address_a[5]
address_a[6] => altsyncram_7vt:auto_generated.address_a[6]
address_a[7] => altsyncram_7vt:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_7vt:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_7vt:auto_generated.q_a[0]
q_a[1] <= altsyncram_7vt:auto_generated.q_a[1]
q_a[2] <= altsyncram_7vt:auto_generated.q_a[2]
q_a[3] <= altsyncram_7vt:auto_generated.q_a[3]
q_a[4] <= altsyncram_7vt:auto_generated.q_a[4]
q_a[5] <= altsyncram_7vt:auto_generated.q_a[5]
q_a[6] <= altsyncram_7vt:auto_generated.q_a[6]
q_a[7] <= altsyncram_7vt:auto_generated.q_a[7]
q_b[0] <= <GND>


|dds|data_juchi:u33|altsyncram:altsyncram_component|altsyncram_7vt:auto_generated
address_a[0] => altsyncram_fnb2:altsyncram1.address_a[0]
address_a[1] => altsyncram_fnb2:altsyncram1.address_a[1]
address_a[2] => altsyncram_fnb2:altsyncram1.address_a[2]
address_a[3] => altsyncram_fnb2:altsyncram1.address_a[3]
address_a[4] => altsyncram_fnb2:altsyncram1.address_a[4]
address_a[5] => altsyncram_fnb2:altsyncram1.address_a[5]
address_a[6] => altsyncram_fnb2:altsyncram1.address_a[6]
address_a[7] => altsyncram_fnb2:altsyncram1.address_a[7]
clock0 => altsyncram_fnb2:altsyncram1.clock0
q_a[0] <= altsyncram_fnb2:altsyncram1.q_a[0]
q_a[1] <= altsyncram_fnb2:altsyncram1.q_a[1]
q_a[2] <= altsyncram_fnb2:altsyncram1.q_a[2]
q_a[3] <= altsyncram_fnb2:altsyncram1.q_a[3]
q_a[4] <= altsyncram_fnb2:altsyncram1.q_a[4]
q_a[5] <= altsyncram_fnb2:altsyncram1.q_a[5]
q_a[6] <= altsyncram_fnb2:altsyncram1.q_a[6]
q_a[7] <= altsyncram_fnb2:altsyncram1.q_a[7]


|dds|data_juchi:u33|altsyncram:altsyncram_component|altsyncram_7vt:auto_generated|altsyncram_fnb2:altsyncram1
address_a[0] => ram_block3a0.PORTAADDR
address_a[0] => ram_block3a1.PORTAADDR
address_a[0] => ram_block3a2.PORTAADDR
address_a[0] => ram_block3a3.PORTAADDR
address_a[0] => ram_block3a4.PORTAADDR
address_a[0] => ram_block3a5.PORTAADDR
address_a[0] => ram_block3a6.PORTAADDR
address_a[0] => ram_block3a7.PORTAADDR
address_a[1] => ram_block3a0.PORTAADDR1
address_a[1] => ram_block3a1.PORTAADDR1
address_a[1] => ram_block3a2.PORTAADDR1
address_a[1] => ram_block3a3.PORTAADDR1
address_a[1] => ram_block3a4.PORTAADDR1
address_a[1] => ram_block3a5.PORTAADDR1
address_a[1] => ram_block3a6.PORTAADDR1
address_a[1] => ram_block3a7.PORTAADDR1
address_a[2] => ram_block3a0.PORTAADDR2
address_a[2] => ram_block3a1.PORTAADDR2
address_a[2] => ram_block3a2.PORTAADDR2
address_a[2] => ram_block3a3.PORTAADDR2
address_a[2] => ram_block3a4.PORTAADDR2
address_a[2] => ram_block3a5.PORTAADDR2
address_a[2] => ram_block3a6.PORTAADDR2
address_a[2] => ram_block3a7.PORTAADDR2
address_a[3] => ram_block3a0.PORTAADDR3
address_a[3] => ram_block3a1.PORTAADDR3
address_a[3] => ram_block3a2.PORTAADDR3
address_a[3] => ram_block3a3.PORTAADDR3
address_a[3] => ram_block3a4.PORTAADDR3
address_a[3] => ram_block3a5.PORTAADDR3
address_a[3] => ram_block3a6.PORTAADDR3
address_a[3] => ram_block3a7.PORTAADDR3
address_a[4] => ram_block3a0.PORTAADDR4
address_a[4] => ram_block3a1.PORTAADDR4
address_a[4] => ram_block3a2.PORTAADDR4
address_a[4] => ram_block3a3.PORTAADDR4
address_a[4] => ram_block3a4.PORTAADDR4
address_a[4] => ram_block3a5.PORTAADDR4
address_a[4] => ram_block3a6.PORTAADDR4
address_a[4] => ram_block3a7.PORTAADDR4
address_a[5] => ram_block3a0.PORTAADDR5
address_a[5] => ram_block3a1.PORTAADDR5
address_a[5] => ram_block3a2.PORTAADDR5
address_a[5] => ram_block3a3.PORTAADDR5
address_a[5] => ram_block3a4.PORTAADDR5
address_a[5] => ram_block3a5.PORTAADDR5
address_a[5] => ram_block3a6.PORTAADDR5
address_a[5] => ram_block3a7.PORTAADDR5
address_a[6] => ram_block3a0.PORTAADDR6
address_a[6] => ram_block3a1.PORTAADDR6
address_a[6] => ram_block3a2.PORTAADDR6
address_a[6] => ram_block3a3.PORTAADDR6
address_a[6] => ram_block3a4.PORTAADDR6
address_a[6] => ram_block3a5.PORTAADDR6
address_a[6] => ram_block3a6.PORTAADDR6
address_a[6] => ram_block3a7.PORTAADDR6
address_a[7] => ram_block3a0.PORTAADDR7
address_a[7] => ram_block3a1.PORTAADDR7
address_a[7] => ram_block3a2.PORTAADDR7
address_a[7] => ram_block3a3.PORTAADDR7
address_a[7] => ram_block3a4.PORTAADDR7
address_a[7] => ram_block3a5.PORTAADDR7
address_a[7] => ram_block3a6.PORTAADDR7
address_a[7] => ram_block3a7.PORTAADDR7
address_b[0] => ram_block3a0.PORTBADDR
address_b[0] => ram_block3a1.PORTBADDR
address_b[0] => ram_block3a2.PORTBADDR
address_b[0] => ram_block3a3.PORTBADDR
address_b[0] => ram_block3a4.PORTBADDR
address_b[0] => ram_block3a5.PORTBADDR
address_b[0] => ram_block3a6.PORTBADDR
address_b[0] => ram_block3a7.PORTBADDR
address_b[1] => ram_block3a0.PORTBADDR1
address_b[1] => ram_block3a1.PORTBADDR1
address_b[1] => ram_block3a2.PORTBADDR1
address_b[1] => ram_block3a3.PORTBADDR1
address_b[1] => ram_block3a4.PORTBADDR1
address_b[1] => ram_block3a5.PORTBADDR1
address_b[1] => ram_block3a6.PORTBADDR1
address_b[1] => ram_block3a7.PORTBADDR1
address_b[2] => ram_block3a0.PORTBADDR2
address_b[2] => ram_block3a1.PORTBADDR2
address_b[2] => ram_block3a2.PORTBADDR2
address_b[2] => ram_block3a3.PORTBADDR2
address_b[2] => ram_block3a4.PORTBADDR2
address_b[2] => ram_block3a5.PORTBADDR2
address_b[2] => ram_block3a6.PORTBADDR2
address_b[2] => ram_block3a7.PORTBADDR2
address_b[3] => ram_block3a0.PORTBADDR3
address_b[3] => ram_block3a1.PORTBADDR3
address_b[3] => ram_block3a2.PORTBADDR3
address_b[3] => ram_block3a3.PORTBADDR3
address_b[3] => ram_block3a4.PORTBADDR3
address_b[3] => ram_block3a5.PORTBADDR3
address_b[3] => ram_block3a6.PORTBADDR3
address_b[3] => ram_block3a7.PORTBADDR3
address_b[4] => ram_block3a0.PORTBADDR4
address_b[4] => ram_block3a1.PORTBADDR4
address_b[4] => ram_block3a2.PORTBADDR4
address_b[4] => ram_block3a3.PORTBADDR4
address_b[4] => ram_block3a4.PORTBADDR4
address_b[4] => ram_block3a5.PORTBADDR4
address_b[4] => ram_block3a6.PORTBADDR4
address_b[4] => ram_block3a7.PORTBADDR4
address_b[5] => ram_block3a0.PORTBADDR5
address_b[5] => ram_block3a1.PORTBADDR5
address_b[5] => ram_block3a2.PORTBADDR5
address_b[5] => ram_block3a3.PORTBADDR5
address_b[5] => ram_block3a4.PORTBADDR5
address_b[5] => ram_block3a5.PORTBADDR5
address_b[5] => ram_block3a6.PORTBADDR5
address_b[5] => ram_block3a7.PORTBADDR5
address_b[6] => ram_block3a0.PORTBADDR6
address_b[6] => ram_block3a1.PORTBADDR6
address_b[6] => ram_block3a2.PORTBADDR6
address_b[6] => ram_block3a3.PORTBADDR6
address_b[6] => ram_block3a4.PORTBADDR6
address_b[6] => ram_block3a5.PORTBADDR6
address_b[6] => ram_block3a6.PORTBADDR6
address_b[6] => ram_block3a7.PORTBADDR6
address_b[7] => ram_block3a0.PORTBADDR7
address_b[7] => ram_block3a1.PORTBADDR7
address_b[7] => ram_block3a2.PORTBADDR7
address_b[7] => ram_block3a3.PORTBADDR7
address_b[7] => ram_block3a4.PORTBADDR7
address_b[7] => ram_block3a5.PORTBADDR7
address_b[7] => ram_block3a6.PORTBADDR7
address_b[7] => ram_block3a7.PORTBADDR7
clock0 => ram_block3a0.CLK0
clock0 => ram_block3a1.CLK0
clock0 => ram_block3a2.CLK0
clock0 => ram_block3a3.CLK0
clock0 => ram_block3a4.CLK0
clock0 => ram_block3a5.CLK0
clock0 => ram_block3a6.CLK0
clock0 => ram_block3a7.CLK0
clock1 => ram_block3a0.CLK1
clock1 => ram_block3a1.CLK1
clock1 => ram_block3a2.CLK1
clock1 => ram_block3a3.CLK1
clock1 => ram_block3a4.CLK1
clock1 => ram_block3a5.CLK1
clock1 => ram_block3a6.CLK1
clock1 => ram_block3a7.CLK1
data_b[0] => ram_block3a0.PORTBDATAIN
data_b[1] => ram_block3a1.PORTBDATAIN
data_b[2] => ram_block3a2.PORTBDATAIN
data_b[3] => ram_block3a3.PORTBDATAIN
data_b[4] => ram_block3a4.PORTBDATAIN
data_b[5] => ram_block3a5.PORTBDATAIN
data_b[6] => ram_block3a6.PORTBDATAIN
data_b[7] => ram_block3a7.PORTBDATAIN
q_a[0] <= ram_block3a0.PORTADATAOUT
q_a[1] <= ram_block3a1.PORTADATAOUT
q_a[2] <= ram_block3a2.PORTADATAOUT
q_a[3] <= ram_block3a3.PORTADATAOUT
q_a[4] <= ram_block3a4.PORTADATAOUT
q_a[5] <= ram_block3a5.PORTADATAOUT
q_a[6] <= ram_block3a6.PORTADATAOUT
q_a[7] <= ram_block3a7.PORTADATAOUT
q_b[0] <= ram_block3a0.PORTBDATAOUT
q_b[1] <= ram_block3a1.PORTBDATAOUT
q_b[2] <= ram_block3a2.PORTBDATAOUT
q_b[3] <= ram_block3a3.PORTBDATAOUT
q_b[4] <= ram_block3a4.PORTBDATAOUT
q_b[5] <= ram_block3a5.PORTBDATAOUT
q_b[6] <= ram_block3a6.PORTBDATAOUT
q_b[7] <= ram_block3a7.PORTBDATAOUT
wren_b => ram_block3a0.PORTBRE
wren_b => ram_block3a1.PORTBRE
wren_b => ram_block3a2.PORTBRE
wren_b => ram_block3a3.PORTBRE
wren_b => ram_block3a4.PORTBRE
wren_b => ram_block3a5.PORTBRE
wren_b => ram_block3a6.PORTBRE
wren_b => ram_block3a7.PORTBRE


|dds|data_juchi:u33|altsyncram:altsyncram_component|altsyncram_7vt:auto_generated|sld_mod_ram_rom:mgl_prim2
tck_usr <= raw_tck.DB_MAX_OUTPUT_PORT_TYPE
address[0] <= ram_rom_addr_reg[0].DB_MAX_OUTPUT_PORT_TYPE
address[1] <= ram_rom_addr_reg[1].DB_MAX_OUTPUT_PORT_TYPE
address[2] <= ram_rom_addr_reg[2].DB_MAX_OUTPUT_PORT_TYPE
address[3] <= ram_rom_addr_reg[3].DB_MAX_OUTPUT_PORT_TYPE
address[4] <= ram_rom_addr_reg[4].DB_MAX_OUTPUT_PORT_TYPE
address[5] <= ram_rom_addr_reg[5].DB_MAX_OUTPUT_PORT_TYPE
address[6] <= ram_rom_addr_reg[6].DB_MAX_OUTPUT_PORT_TYPE
address[7] <= ram_rom_addr_reg[7].DB_MAX_OUTPUT_PORT_TYPE
enable_write <= enable_write~0.DB_MAX_OUTPUT_PORT_TYPE
data_write[0] <= ram_rom_data_reg[0].DB_MAX_OUTPUT_PORT_TYPE
data_write[1] <= ram_rom_data_reg[1].DB_MAX_OUTPUT_PORT_TYPE
data_write[2] <= ram_rom_data_reg[2].DB_MAX_OUTPUT_PORT_TYPE
data_write[3] <= ram_rom_data_reg[3].DB_MAX_OUTPUT_PORT_TYPE
data_write[4] <= ram_rom_data_reg[4].DB_MAX_OUTPUT_PORT_TYPE
data_write[5] <= ram_rom_data_reg[5].DB_MAX_OUTPUT_PORT_TYPE
data_write[6] <= ram_rom_data_reg[6].DB_MAX_OUTPUT_PORT_TYPE
data_write[7] <= ram_rom_data_reg[7].DB_MAX_OUTPUT_PORT_TYPE
data_read[0] => ram_rom_data_reg~15.DATAB
data_read[1] => ram_rom_data_reg~14.DATAB
data_read[2] => ram_rom_data_reg~13.DATAB
data_read[3] => ram_rom_data_reg~12.DATAB
data_read[4] => ram_rom_data_reg~11.DATAB
data_read[5] => ram_rom_data_reg~10.DATAB
data_read[6] => ram_rom_data_reg~9.DATAB
data_read[7] => ram_rom_data_reg~8.DATAB
raw_tck => ram_rom_addr_reg[6].CLK
raw_tck => ram_rom_addr_reg[5].CLK
raw_tck => ram_rom_addr_reg[4].CLK
raw_tck => ram_rom_addr_reg[3].CLK
raw_tck => ram_rom_addr_reg[2].CLK
raw_tck => ram_rom_addr_reg[1].CLK
raw_tck => ram_rom_addr_reg[0].CLK
raw_tck => ram_rom_data_reg[7].CLK
raw_tck => ram_rom_data_reg[6].CLK