dds.hier_info

多功能函数发生器

|dds
clk => data_sin:u34.inclock
clk => data_juchi:u33.inclock
clk => data_f:u32.inclock
clk => data_v:u31.inclock
clk => adder:u1.load
f_c[0] => adder:u1.a[2]
f_c[1] => adder:u1.a[3]
f_c[2] => adder:u1.a[4]
f_c[3] => adder:u1.a[5]
f_c[4] => adder:u1.a[6]
f_c[5] => adder:u1.a[7]
s_out[0] <= d_switch:u2.sw_out[0]
s_out[1] <= d_switch:u2.sw_out[1]
s_out[2] <= d_switch:u2.sw_out[2]
s_out[3] <= d_switch:u2.sw_out[3]
s_out[4] <= d_switch:u2.sw_out[4]
s_out[5] <= d_switch:u2.sw_out[5]
s_out[6] <= d_switch:u2.sw_out[6]
s_out[7] <= d_switch:u2.sw_out[7]
switch[0] => d_switch:u2.c_switch[0]
switch[1] => d_switch:u2.c_switch[1]


|dds|adder:u1
load => s[14]~reg0.CLK
load => s[13]~reg0.CLK
load => s[12]~reg0.CLK
load => s[11]~reg0.CLK
load => s[10]~reg0.CLK
load => s[9]~reg0.CLK
load => s[8]~reg0.CLK
load => s[7]~reg0.CLK
load => s[6]~reg0.CLK
load => s[5]~reg0.CLK
load => s[4]~reg0.CLK
load => s[3]~reg0.CLK
load => s[2]~reg0.CLK
load => s[1]~reg0.CLK
load => s[0]~reg0.CLK
load => s[15]~reg0.CLK
a[0] => add~0.IN16
a[1] => add~0.IN15
a[2] => add~0.IN14
a[3] => add~0.IN13
a[4] => add~0.IN12
a[5] => add~0.IN11
a[6] => add~0.IN10
a[7] => add~0.IN9
a[8] => add~0.IN8
a[9] => add~0.IN7
a[10] => add~0.IN6
a[11] => add~0.IN5
a[12] => add~0.IN4
a[13] => add~0.IN3
a[14] => add~0.IN2
a[15] => add~0.IN1
b[0] => add~0.IN32
b[1] => add~0.IN31
b[2] => add~0.IN30
b[3] => add~0.IN29
b[4] => add~0.IN28
b[5] => add~0.IN27
b[6] => add~0.IN26
b[7] => add~0.IN25
b[8] => add~0.IN24
b[9] => add~0.IN23
b[10] => add~0.IN22
b[11] => add~0.IN21
b[12] => add~0.IN20
b[13] => add~0.IN19
b[14] => add~0.IN18
b[15] => add~0.IN17
s[0] <= s[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s[1] <= s[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s[2] <= s[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s[3] <= s[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s[4] <= s[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s[5] <= s[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s[6] <= s[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s[7] <= s[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s[8] <= s[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s[9] <= s[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s[10] <= s[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s[11] <= s[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s[12] <= s[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s[13] <= s[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s[14] <= s[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s[15] <= s[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|dds|d_switch:u2
sw_out[0] <= Mux~7.DB_MAX_OUTPUT_PORT_TYPE
sw_out[1] <= Mux~6.DB_MAX_OUTPUT_PORT_TYPE
sw_out[2] <= Mux~5.DB_MAX_OUTPUT_PORT_TYPE
sw_out[3] <= Mux~4.DB_MAX_OUTPUT_PORT_TYPE
sw_out[4] <= Mux~3.DB_MAX_OUTPUT_PORT_TYPE
sw_out[5] <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
sw_out[6] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
sw_out[7] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE
sw_in0[0] => Mux~7.IN0
sw_in0[1] => Mux~6.IN0
sw_in0[2] => Mux~5.IN0
sw_in0[3] => Mux~4.IN0
sw_in0[4] => Mux~3.IN0
sw_in0[5] => Mux~2.IN0
sw_in0[6] => Mux~1.IN0
sw_in0[7] => Mux~0.IN0
sw_in1[0] => Mux~7.IN1
sw_in1[1] => Mux~6.IN1
sw_in1[2] => Mux~5.IN1
sw_in1[3] => Mux~4.IN1
sw_in1[4] => Mux~3.IN1
sw_in1[5] => Mux~2.IN1
sw_in1[6] => Mux~1.IN1
sw_in1[7] => Mux~0.IN1
sw_in2[0] => Mux~7.IN2
sw_in2[1] => Mux~6.IN2
sw_in2[2] => Mux~5.IN2
sw_in2[3] => Mux~4.IN2
sw_in2[4] => Mux~3.IN2
sw_in2[5] => Mux~2.IN2
sw_in2[6] => Mux~1.IN2
sw_in2[7] => Mux~0.IN2
sw_in3[0] => Mux~7.IN3
sw_in3[1] => Mux~6.IN3
sw_in3[2] => Mux~5.IN3
sw_in3[3] => Mux~4.IN3
sw_in3[4] => Mux~3.IN3
sw_in3[5] => Mux~2.IN3
sw_in3[6] => Mux~1.IN3
sw_in3[7] => Mux~0.IN3
c_switch[0] => Mux~0.IN5
c_switch[0] => Mux~1.IN5
c_switch[0] => Mux~2.IN5
c_switch[0] => Mux~3.IN5
c_switch[0] => Mux~4.IN5
c_switch[0] => Mux~5.IN5
c_switch[0] => Mux~6.IN5
c_switch[0] => Mux~7.IN5
c_switch[1] => Mux~0.IN4
c_switch[1] => Mux~1.IN4
c_switch[1] => Mux~2.IN4
c_switch[1] => Mux~3.IN4
c_switch[1] => Mux~4.IN4
c_switch[1] => Mux~5.IN4
c_switch[1] => Mux~6.IN4
c_switch[1] => Mux~7.IN4


|dds|data_v:u31
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
inclock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]


|dds|data_v:u31|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_8it:auto_generated.address_a[0]
address_a[1] => altsyncram_8it:auto_generated.address_a[1]
address_a[2] => altsyncram_8it:auto_generated.address_a[2]
address_a[3] => altsyncram_8it:auto_generated.address_a[3]
address_a[4] => altsyncram_8it:auto_generated.address_a[4]
address_a[5] => altsyncram_8it:auto_generated.address_a[5]
address_a[6] => altsyncram_8it:auto_generated.address_a[6]
address_a[7] => altsyncram_8it:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_8it:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_8it:auto_generated.q_a[0]
q_a[1] <= altsyncram_8it:auto_generated.q_a[1]
q_a[2] <= altsyncram_8it:auto_generated.q_a[2]
q_a[3] <= altsyncram_8it:auto_generated.q_a[3]
q_a[4] <= altsyncram_8it:auto_generated.q_a[4]
q_a[5] <= altsyncram_8it:auto_generated.q_a[5]
q_a[6] <= altsyncram_8it:auto_generated.q_a[6]
q_a[7] <= altsyncram_8it:auto_generated.q_a[7]
q_b[0] <= <GND>


|dds|data_v:u31|altsyncram:altsyncram_component|altsyncram_8it:auto_generated
address_a[0] => altsyncram_iab2:altsyncram1.address_a[0]
address_a[1] => altsyncram_iab2:altsyncram1.address_a[1]
address_a[2] => altsyncram_iab2:altsyncram1.address_a[2]
address_a[3] => altsyncram_iab2:altsyncram1.address_a[3]
address_a[4] => altsyncram_iab2:altsyncram1.address_a[4]
address_a[5] => altsyncram_iab2:altsyncram1.address_a[5]
address_a[6] => altsyncram_iab2:altsyncram1.address_a[6]
address_a[7] => altsyncram_iab2:altsyncram1.address_a[7]
clock0 => altsyncram_iab2:altsyncram1.clock0
q_a[0] <= altsyncram_iab2:altsyncram1.q_a[0]
q_a[1] <= altsyncram_iab2:altsyncram1.q_a[1]
q_a[2] <= altsyncram_iab2:altsyncram1.q_a[2]
q_a[3] <= altsyncram_iab2:altsyncram1.q_a[3]
q_a[4] <= altsyncram_iab2:altsyncram1.q_a[4]
q_a[5] <= altsyncram_iab2:altsyncram1.q_a[5]
q_a[6] <= altsyncram_iab2:altsyncram1.q_a[6]
q_a[7] <= altsyncram_iab2:altsyncram1.q_a[7]


|dds|data_v:u31|altsyncram:altsyncram_component|altsyncram_8it:auto_generated|altsyncram_iab2:altsyncram1
address_a[0] => ram_block3a0.PORTAADDR
address_a[0] => ram_block3a1.PORTAADDR
address_a[0] => ram_block3a2.PORTAADDR
address_a[0] => ram_block3a3.PORTAADDR
address_a[0] => ram_block3a4.PORTAADDR
address_a[0] => ram_block3a5.PORTAADDR
address_a[0] => ram_block3a6.PORTAADDR
address_a[0] => ram_block3a7.PORTAADDR
address_a[1] => ram_block3a0.PORTAADDR1
address_a[1] => ram_block3a1.PORTAADDR1
address_a[1] => ram_block3a2.PORTAADDR1
address_a[1] => ram_block3a3.PORTAADDR1
address_a[1] => ram_block3a4.PORTAADDR1
address_a[1] => ram_block3a5.PORTAADDR1
address_a[1] => ram_block3a6.PORTAADDR1
address_a[1] => ram_block3a7.PORTAADDR1
address_a[2] => ram_block3a0.PORTAADDR2
address_a[2] => ram_block3a1.PORTAADDR2
address_a[2] => ram_block3a2.PORTAADDR2
address_a[2] => ram_block3a3.PORTAADDR2
address_a[2] => ram_block3a4.PORTAADDR2
address_a[2] => ram_block3a5.PORTAADDR2
address_a[2] => ram_block3a6.PORTAADDR2
address_a[2] => ram_block3a7.PORTAADDR2
address_a[3] => ram_block3a0.PORTAADDR3
address_a[3] => ram_block3a1.PORTAADDR3
address_a[3] => ram_block3a2.PORTAADDR3
address_a[3] => ram_block3a3.PORTAADDR3
address_a[3] => ram_block3a4.PORTAADDR3
address_a[3] => ram_block3a5.PORTAADDR3
address_a[3] => ram_block3a6.PORTAADDR3
address_a[3] => ram_block3a7.PORTAADDR3
address_a[4] => ram_block3a0.PORTAADDR4
address_a[4] => ram_block3a1.PORTAADDR4
address_a[4] => ram_block3a2.PORTAADDR4
address_a[4] => ram_block3a3.PORTAADDR4
address_a[4] => ram_block3a4.PORTAADDR4
address_a[4] => ram_block3a5.PORTAADDR4
address_a[4] => ram_block3a6.PORTAADDR4
address_a[4] => ram_block3a7.PORTAADDR4
address_a[5] => ram_block3a0.PORTAADDR5
address_a[5] => ram_block3a1.PORTAADDR5
address_a[5] => ram_block3a2.PORTAADDR5
address_a[5] => ram_block3a3.PORTAADDR5
address_a[5] => ram_block3a4.PORTAADDR5
address_a[5] => ram_block3a5.PORTAADDR5
address_a[5] => ram_block3a6.PORTAADDR5
address_a[5] => ram_block3a7.PORTAADDR5
address_a[6] => ram_block3a0.PORTAADDR6
address_a[6] => ram_block3a1.PORTAADDR6
address_a[6] => ram_block3a2.PORTAADDR6
address_a[6] => ram_block3a3.PORTAADDR6
address_a[6] => ram_block3a4.PORTAADDR6
address_a[6] => ram_block3a5.PORTAADDR6
address_a[6] => ram_block3a6.PORTAADDR6
address_a[6] => ram_block3a7.PORTAADDR6
address_a[7] => ram_block3a0.PORTAADDR7
address_a[7] => ram_block3a1.PORTAADDR7
address_a[7] => ram_block3a2.PORTAADDR7
address_a[7] => ram_block3a3.PORTAADDR7
address_a[7] => ram_block3a4.PORTAADDR7
address_a[7] => ram_block3a5.PORTAADDR7
address_a[7] => ram_block3a6.PORTAADDR7
address_a[7] => ram_block3a7.PORTAADDR7
address_b[0] => ram_block3a0.PORTBADDR
address_b[0] => ram_block3a1.PORTBADDR
address_b[0] => ram_block3a2.PORTBADDR
address_b[0] => ram_block3a3.PORTBADDR
address_b[0] => ram_block3a4.PORTBADDR
address_b[0] => ram_block3a5.PORTBADDR
address_b[0] => ram_block3a6.PORTBADDR
address_b[0] => ram_block3a7.PORTBADDR
address_b[1] => ram_block3a0.PORTBADDR1
address_b[1] => ram_block3a1.PORTBADDR1
address_b[1] => ram_block3a2.PORTBADDR1
address_b[1] => ram_block3a3.PORTBADDR1
address_b[1] => ram_block3a4.PORTBADDR1
address_b[1] => ram_block3a5.PORTBADDR1
address_b[1] => ram_block3a6.PORTBADDR1
address_b[1] => ram_block3a7.PORTBADDR1
address_b[2] => ram_block3a0.PORTBADDR2
address_b[2] => ram_block3a1.PORTBADDR2
address_b[2] => ram_block3a2.PORTBADDR2
address_b[2] => ram_block3a3.PORTBADDR2
address_b[2] => ram_block3a4.PORTBADDR2
address_b[2] => ram_block3a5.PORTBADDR2
address_b[2] => ram_block3a6.PORTBADDR2
address_b[2] => ram_block3a7.PORTBADDR2
address_b[3] => ram_block3a0.PORTBADDR3
address_b[3] => ram_block3a1.PORTBADDR3
address_b[3] => ram_block3a2.PORTBADDR3
address_b[3] => ram_block3a3.PORTBADDR3
address_b[3] => ram_block3a4.PORTBADDR3
address_b[3] => ram_block3a5.PORTBADDR3
address_b[3] => ram_block3a6.PORTBADDR3
address_b[3] => ram_block3a7.PORTBADDR3
address_b[4] => ram_block3a0.PORTBADDR4
address_b[4] => ram_block3a1.PORTBADDR4
address_b[4] => ram_block3a2.PORTBADDR4
address_b[4] => ram_block3a3.PORTBADDR4
address_b[4] => ram_block3a4.PORTBADDR4
address_b[4] => ram_block3a5.PORTBADDR4
address_b[4] => ram_block3a6.PORTBADDR4
address_b[4] => ram_block3a7.PORTBADDR4
address_b[5] => ram_block3a0.PORTBADDR5
address_b[5] => ram_block3a1.PORTBADDR5
address_b[5] => ram_block3a2.PORTBADDR5
address_b[5] => ram_block3a3.PORTBADDR5
address_b[5] => ram_block3a4.PORTBADDR5
address_b[5] => ram_block3a5.PORTBADDR5
address_b[5] => ram_block3a6.PORTBADDR5
address_b[5] => ram_block3a7.PORTBADDR5
address_b[6] => ram_block3a0.PORTBADDR6
address_b[6] => ram_block3a1.PORTBADDR6
address_b[6] => ram_block3a2.PORTBADDR6
address_b[6] => ram_block3a3.PORTBADDR6
address_b[6] => ram_block3a4.PORTBADDR6