dds.hif

多功能函数发生器

USR
is_data_in_ram
1
PARAMETER_UNKNOWN
USR
is_readable
1
PARAMETER_UNKNOWN
USR
node_name
1380928817
PARAMETER_UNKNOWN
USR
}
# include_file {
d:|program files|altera|quartus50|libraries|megafunctions|sld_mod_ram_rom.vhd
1114012240
}
# hierarchies {
data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|sld_mod_ram_rom:mgl_prim2
}
# end
# entity
sld_hub
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
d:|program files|altera|quartus50|libraries|megafunctions|sld_hub.vhd
1114012238
4
# storage
db|dds.(24).cnf
db|dds.(24).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
sld_hub_ip_version
1
PARAMETER_UNKNOWN
USR
sld_hub_ip_minor_version
2
PARAMETER_UNKNOWN
USR
sld_common_ip_version
0
PARAMETER_UNKNOWN
USR
device_family
Cyclone
PARAMETER_UNKNOWN
USR
n_nodes
4
PARAMETER_UNKNOWN
USR
n_sel_bits
3
PARAMETER_UNKNOWN
USR
n_node_ir_bits
6
PARAMETER_UNKNOWN
USR
node_info
00001000000110000110111000000011000010000001100001101110000000100000100000011000011011100000000100001000000110000110111000000000
PARAMETER_BIN
USR
}
# include_file {
d:|program files|altera|quartus50|libraries|megafunctions|sld_hub.vhd
1114012238
}
# end
# entity
sld_jtag_state_machine
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
d:|program files|altera|quartus50|libraries|megafunctions|sld_hub.vhd
1114012238
4
# storage
db|dds.(25).cnf
db|dds.(25).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
1
PARAMETER_DEC
USR
ip_minor_version
2
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
}
# include_file {
d:|program files|altera|quartus50|libraries|megafunctions|sld_hub.vhd
1114012238
}
# end
# entity
lpm_shiftreg
# case_insensitive
# source_file
d:|program files|altera|quartus50|libraries|megafunctions|lpm_shiftreg.tdf
1114012454
6
# storage
db|dds.(26).cnf
db|dds.(26).cnf
# user_parameter {
LPM_WIDTH
10
PARAMETER_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clock
enable
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
shiftin
}
# include_file {
d:|program files|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
d:|program files|altera|quartus50|libraries|megafunctions|dffeea.inc
1107574164
d:|program files|altera|quartus50|libraries|megafunctions|lpm_constant.inc
1107574524
}
# end
# entity
lpm_decode
# case_insensitive
# source_file
d:|program files|altera|quartus50|libraries|megafunctions|lpm_decode.tdf
1114012450
6
# storage
db|dds.(27).cnf
db|dds.(27).cnf
# user_parameter {
LPM_WIDTH
3
PARAMETER_DEC
USR
LPM_DECODES
8
PARAMETER_DEC
USR
LPM_PIPELINE
1
PARAMETER_DEC
USR
CASCADE_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
decode_9ie
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clken
clock
data0
data1
data2
enable
eq0
eq1
eq2
eq3
eq7
}
# include_file {
d:|program files|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
d:|program files|altera|quartus50|libraries|megafunctions|lpm_constant.inc
1107574524
d:|program files|altera|quartus50|libraries|megafunctions|declut.inc
1107574136
d:|program files|altera|quartus50|libraries|megafunctions|altshift.inc
1107573438
d:|program files|altera|quartus50|libraries|megafunctions|lpm_compare.inc
1107574500
}
# end
# entity
decode_9ie
# case_insensitive
# source_file
db|decode_9ie.tdf
1215750317
6
# storage
db|dds.(28).cnf
db|dds.(28).cnf
# used_port {
aclr
clken
clock
data0
data1
data2
enable
eq0
eq1
eq2
eq3
eq4
eq5
eq6
eq7
}
# end
# entity
sld_dffex
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
d:|program files|altera|quartus50|libraries|megafunctions|sld_dffex.vhd
1114012236
4
# storage
db|dds.(29).cnf
db|dds.(29).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
1
PARAMETER_DEC
USR
}
# end
# entity
sld_dffex
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
d:|program files|altera|quartus50|libraries|megafunctions|sld_dffex.vhd
1114012236
4
# storage
db|dds.(30).cnf
db|dds.(30).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
9
PARAMETER_DEC
USR
}
# end
# entity
sld_dffex
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
d:|program files|altera|quartus50|libraries|megafunctions|sld_dffex.vhd
1114012236
4
# storage
db|dds.(31).cnf
db|dds.(31).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
6
PARAMETER_DEC
USR
}
# end
# entity
sld_dffex
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
d:|program files|altera|quartus50|libraries|megafunctions|sld_dffex.vhd
1114012236
4
# storage
db|dds.(32).cnf
db|dds.(32).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
4
PARAMETER_DEC
USR
}
# end
# entity
sld_rom_sr
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
d:|program files|altera|quartus50|libraries|megafunctions|sld_rom_sr.vhd
1114012236
4
# storage
db|dds.(33).cnf
db|dds.(33).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
common_ip_version
0
PARAMETER_DEC
USR
n_bits
160
PARAMETER_DEC
USR
word_size
4
PARAMETER_DEC
USR
}
# end
# entity
dds
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
dds.vhd
1216006205
4
# storage
db|dds.(0).cnf
db|dds.(0).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
|
}
# end
# entity
d_switch
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
d_switch.vhd
1216007473
4
# storage
db|dds.(2).cnf
db|dds.(2).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
d_switch:u2
}
# end
# entity
data_v
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
data_v.vhd
1216008223
4
# storage
db|dds.(3).cnf
db|dds.(3).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
data_v:u31
}
# end
# entity
altsyncram
# case_insensitive
# source_file
d:|program files|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|dds.(6).cnf
db|dds.(6).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
8
PARAMETER_DEC
USR
NUMWORDS_A
256
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
./data_rom/data_v.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_8it
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
}
# include_file {
d:|program files|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
d:|program files|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
d:|program files|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
d:|program files|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
d:|program files|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
d:|program files|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
d:|program files|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
d:|program files|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
d:|program files|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
d:|program files|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
}
# hierarchies {
data_v:u31|altsyncram:altsyncram_component
}
# end
# entity
altsyncram_8it
# case_insensitive
# source_file
db|altsyncram_8it.tdf
1216008284
6
# storage
db|dds.(34).cnf
db|dds.(34).cnf
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
}
# hierarchies {
data_v:u31|altsyncram:altsyncram_component|altsyncram_8it:auto_generated
}
# end
# entity
altsyncram_iab2
# case_insensitive
# source_file
db|altsyncram_iab2.tdf
1216008284
6
# storage
db|dds.(35).cnf
db|dds.(35).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
address_b6
address_b7
clock0
clock1
data_b0
data_b1
data_b2
data_b3
data_b4
data_b5
data_b6
data_b7
wren_b
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
}
# memory_file {
.|data_rom|data_v.mif
1215334424
}
# hierarchies {
data_v:u31|altsyncram:altsyncram_component|altsyncram_8it:auto_generated|altsyncram_iab2:altsyncram1
}
# end
# complete