dds.hif

多功能函数发生器

Version 5.0 Build 148 04/26/2005 SJ Full Version
32
1595
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
0
# entity
adder
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
adder.vhd
1213612762
4
# storage
db|dds.(1).cnf
db|dds.(1).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
adder:u1
}
# end
# entity
altsyncram
# case_insensitive
# source_file
d:|program files|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|dds.(4).cnf
db|dds.(4).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
8
PARAMETER_DEC
USR
NUMWORDS_A
256
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
.data_rom/data_v.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_pgt
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
}
# include_file {
d:|program files|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
d:|program files|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
d:|program files|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
d:|program files|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
d:|program files|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
d:|program files|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
d:|program files|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
d:|program files|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
d:|program files|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
d:|program files|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
}
# end
# entity
altsyncram_pgt
# case_insensitive
# source_file
db|altsyncram_pgt.tdf
1215750314
6
# storage
db|dds.(5).cnf
db|dds.(5).cnf
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
}
# end
# entity
sld_mod_ram_rom
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
d:|program files|altera|quartus50|libraries|megafunctions|sld_mod_ram_rom.vhd
1114012240
4
# storage
db|dds.(7).cnf
db|dds.(7).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
sld_node_info
135818752
PARAMETER_DEC
DEF
sld_ip_version
1
PARAMETER_DEC
DEF
sld_ip_minor_version
0
PARAMETER_DEC
DEF
sld_common_ip_version
0
PARAMETER_DEC
DEF
width_word
8
PARAMETER_UNKNOWN
USR
numwords
256
PARAMETER_UNKNOWN
USR
widthad
8
PARAMETER_UNKNOWN
USR
shift_count_bits
4
PARAMETER_UNKNOWN
USR
cvalue
00000000
PARAMETER_UNKNOWN
USR
is_data_in_ram
1
PARAMETER_UNKNOWN
USR
is_readable
1
PARAMETER_UNKNOWN
USR
node_name
1380928818
PARAMETER_UNKNOWN
USR
}
# include_file {
d:|program files|altera|quartus50|libraries|megafunctions|sld_mod_ram_rom.vhd
1114012240
}
# hierarchies {
data_v:u31|altsyncram:altsyncram_component|altsyncram_8it:auto_generated|sld_mod_ram_rom:mgl_prim2
}
# end
# entity
sld_rom_sr
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
d:|program files|altera|quartus50|libraries|megafunctions|sld_rom_sr.vhd
1114012236
4
# storage
db|dds.(8).cnf
db|dds.(8).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
common_ip_version
0
PARAMETER_DEC
USR
n_bits
80
PARAMETER_DEC
USR
word_size
4
PARAMETER_DEC
USR
}
# hierarchies {
data_v:u31|altsyncram:altsyncram_component|altsyncram_8it:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
data_juchi:u33|altsyncram:altsyncram_component|altsyncram_7vt:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
}
# end
# entity
data_f
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
data_f.vhd
1215353790
4
# storage
db|dds.(9).cnf
db|dds.(9).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
data_f:u32
}
# end
# entity
altsyncram
# case_insensitive
# source_file
d:|program files|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|dds.(10).cnf
db|dds.(10).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
8
PARAMETER_DEC
USR
NUMWORDS_A
256
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
./data_rom/data_f.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_pht
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
}
# include_file {
d:|program files|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
d:|program files|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
d:|program files|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
d:|program files|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
d:|program files|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
d:|program files|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
d:|program files|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
d:|program files|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
d:|program files|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
d:|program files|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
}
# hierarchies {
data_f:u32|altsyncram:altsyncram_component
}
# end
# entity
altsyncram_pht
# case_insensitive
# source_file
db|altsyncram_pht.tdf
1215750315
6
# storage
db|dds.(11).cnf
db|dds.(11).cnf
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
}
# hierarchies {
data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated
}
# end
# entity
altsyncram_2ab2
# case_insensitive
# source_file
db|altsyncram_2ab2.tdf
1215750315
6
# storage
db|dds.(12).cnf
db|dds.(12).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
address_b6
address_b7
clock0
clock1
data_b0
data_b1
data_b2
data_b3
data_b4
data_b5
data_b6
data_b7
wren_b
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
}
# memory_file {
.|data_rom|data_f.mif
1215335034
}
# hierarchies {
data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1
}
# end
# entity
sld_mod_ram_rom
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
d:|program files|altera|quartus50|libraries|megafunctions|sld_mod_ram_rom.vhd
1114012240
4
# storage
db|dds.(13).cnf
db|dds.(13).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
sld_node_info
135818752
PARAMETER_DEC
DEF
sld_ip_version
1
PARAMETER_DEC
DEF
sld_ip_minor_version
0
PARAMETER_DEC
DEF
sld_common_ip_version
0
PARAMETER_DEC
DEF
width_word
8
PARAMETER_UNKNOWN
USR
numwords
256
PARAMETER_UNKNOWN
USR
widthad
8
PARAMETER_UNKNOWN
USR
shift_count_bits
4
PARAMETER_UNKNOWN
USR
cvalue
00000000
PARAMETER_UNKNOWN
USR
is_data_in_ram
1
PARAMETER_UNKNOWN
USR
is_readable
1
PARAMETER_UNKNOWN
USR
node_name
1380928819
PARAMETER_UNKNOWN
USR
}
# include_file {
d:|program files|altera|quartus50|libraries|megafunctions|sld_mod_ram_rom.vhd
1114012240
}
# hierarchies {
data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|sld_mod_ram_rom:mgl_prim2
}
# end
# entity
data_juchi
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
data_juchi.vhd