dds.map.qmsg

多功能函数发生器

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_2ab2.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_2ab2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_2ab2 " "Info: Found entity 1: altsyncram_2ab2" {  } { { "db/altsyncram_2ab2.tdf" "" { Text "G:/eda/qdds/db/altsyncram_2ab2.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_2ab2 data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|altsyncram_2ab2:altsyncram1 " "Info: Elaborating entity \"altsyncram_2ab2\" for hierarchy \"data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|altsyncram_2ab2:altsyncram1\"" {  } { { "db/altsyncram_pht.tdf" "altsyncram1" { Text "G:/eda/qdds/db/altsyncram_pht.tdf" 34 2 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_mod_ram_rom data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Elaborating entity \"sld_mod_ram_rom\" for hierarchy \"data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|sld_mod_ram_rom:mgl_prim2\"" {  } { { "db/altsyncram_pht.tdf" "mgl_prim2" { Text "G:/eda/qdds/db/altsyncram_pht.tdf" 35 2 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "data_juchi.vhd 2 1 " "Info: Using design file data_juchi.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 data_juchi-SYN " "Info: Found design unit 1: data_juchi-SYN" {  } { { "data_juchi.vhd" "" { Text "G:/eda/qdds/data_juchi.vhd" 49 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 data_juchi " "Info: Found entity 1: data_juchi" {  } { { "data_juchi.vhd" "" { Text "G:/eda/qdds/data_juchi.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_juchi data_juchi:u33 " "Info: Elaborating entity \"data_juchi\" for hierarchy \"data_juchi:u33\"" {  } { { "dds.vhd" "u33" { Text "G:/eda/qdds/dds.vhd" 67 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram data_juchi:u33\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"data_juchi:u33\|altsyncram:altsyncram_component\"" {  } { { "data_juchi.vhd" "altsyncram_component" { Text "G:/eda/qdds/data_juchi.vhd" 80 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_7vt.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_7vt.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_7vt " "Info: Found entity 1: altsyncram_7vt" {  } { { "db/altsyncram_7vt.tdf" "" { Text "G:/eda/qdds/db/altsyncram_7vt.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_7vt data_juchi:u33\|altsyncram:altsyncram_component\|altsyncram_7vt:auto_generated " "Info: Elaborating entity \"altsyncram_7vt\" for hierarchy \"data_juchi:u33\|altsyncram:altsyncram_component\|altsyncram_7vt:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/program files/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_fnb2.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_fnb2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_fnb2 " "Info: Found entity 1: altsyncram_fnb2" {  } { { "db/altsyncram_fnb2.tdf" "" { Text "G:/eda/qdds/db/altsyncram_fnb2.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_fnb2 data_juchi:u33\|altsyncram:altsyncram_component\|altsyncram_7vt:auto_generated\|altsyncram_fnb2:altsyncram1 " "Info: Elaborating entity \"altsyncram_fnb2\" for hierarchy \"data_juchi:u33\|altsyncram:altsyncram_component\|altsyncram_7vt:auto_generated\|altsyncram_fnb2:altsyncram1\"" {  } { { "db/altsyncram_7vt.tdf" "altsyncram1" { Text "G:/eda/qdds/db/altsyncram_7vt.tdf" 34 2 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_mod_ram_rom data_juchi:u33\|altsyncram:altsyncram_component\|altsyncram_7vt:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Elaborating entity \"sld_mod_ram_rom\" for hierarchy \"data_juchi:u33\|altsyncram:altsyncram_component\|altsyncram_7vt:auto_generated\|sld_mod_ram_rom:mgl_prim2\"" {  } { { "db/altsyncram_7vt.tdf" "mgl_prim2" { Text "G:/eda/qdds/db/altsyncram_7vt.tdf" 35 2 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "data_sin.vhd 2 1 " "Info: Using design file data_sin.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 data_sin-SYN " "Info: Found design unit 1: data_sin-SYN" {  } { { "data_sin.vhd" "" { Text "G:/eda/qdds/data_sin.vhd" 49 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 data_sin " "Info: Found entity 1: data_sin" {  } { { "data_sin.vhd" "" { Text "G:/eda/qdds/data_sin.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_sin data_sin:u34 " "Info: Elaborating entity \"data_sin\" for hierarchy \"data_sin:u34\"" {  } { { "dds.vhd" "u34" { Text "G:/eda/qdds/dds.vhd" 68 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram data_sin:u34\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"data_sin:u34\|altsyncram:altsyncram_component\"" {  } { { "data_sin.vhd" "altsyncram_component" { Text "G:/eda/qdds/data_sin.vhd" 80 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_rot.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_rot.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_rot " "Info: Found entity 1: altsyncram_rot" {  } { { "db/altsyncram_rot.tdf" "" { Text "G:/eda/qdds/db/altsyncram_rot.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_rot data_sin:u34\|altsyncram:altsyncram_component\|altsyncram_rot:auto_generated " "Info: Elaborating entity \"altsyncram_rot\" for hierarchy \"data_sin:u34\|altsyncram:altsyncram_component\|altsyncram_rot:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/program files/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_6hb2.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_6hb2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_6hb2 " "Info: Found entity 1: altsyncram_6hb2" {  } { { "db/altsyncram_6hb2.tdf" "" { Text "G:/eda/qdds/db/altsyncram_6hb2.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_6hb2 data_sin:u34\|altsyncram:altsyncram_component\|altsyncram_rot:auto_generated\|altsyncram_6hb2:altsyncram1 " "Info: Elaborating entity \"altsyncram_6hb2\" for hierarchy \"data_sin:u34\|altsyncram:altsyncram_component\|altsyncram_rot:auto_generated\|altsyncram_6hb2:altsyncram1\"" {  } { { "db/altsyncram_rot.tdf" "altsyncram1" { Text "G:/eda/qdds/db/altsyncram_rot.tdf" 34 2 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_mod_ram_rom data_sin:u34\|altsyncram:altsyncram_component\|altsyncram_rot:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Elaborating entity \"sld_mod_ram_rom\" for hierarchy \"data_sin:u34\|altsyncram:altsyncram_component\|altsyncram_rot:auto_generated\|sld_mod_ram_rom:mgl_prim2\"" {  } { { "db/altsyncram_rot.tdf" "mgl_prim2" { Text "G:/eda/qdds/db/altsyncram_rot.tdf" 35 2 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd 6 2 " "Info: Found 6 design units, including 2 entities, in source file d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 HUB_PACK " "Info: Found design unit 1: HUB_PACK" {  } { { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 49 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 JTAG_PACK " "Info: Found design unit 2: JTAG_PACK" {  } { { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 63 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 sld_hub-rtl " "Info: Found design unit 3: sld_hub-rtl" {  } { { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 166 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 sld_jtag_state_machine-rtl " "Info: Found design unit 4: sld_jtag_state_machine-rtl" {  } { { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1012 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_hub " "Info: Found entity 1: sld_hub" {  } { { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 99 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_jtag_state_machine " "Info: Found entity 2: sld_jtag_state_machine" {  } { { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 997 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_shiftreg " "Info: Found entity 1: lpm_shiftreg" {  } { { "lpm_shiftreg.tdf" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf" 37 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus50/libraries/megafunctions/lpm_decode.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus50/libraries/megafunctions/lpm_decode.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_decode " "Info: Found entity 1: lpm_decode" {  } { { "lpm_decode.tdf" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/lpm_decode.tdf" 62 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_9ie.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_9ie.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_9ie " "Info: Found entity 1: decode_9ie" {  } { { "db/decode_9ie.tdf" "" { Text "G:/eda/qdds/db/decode_9ie.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_dffex-DFFEX " "Info: Found design unit 1: sld_dffex-DFFEX" {  } { { "sld_dffex.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_dffex " "Info: Found entity 1: sld_dffex" {  } { { "sld_dffex.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adder:u1\|s\[1\] data_in GND " "Warning: Reduced register \"adder:u1\|s\[1\]\" with stuck data_in port to stuck value GND" {  } { { "adder.vhd" "" { Text "G:/eda/qdds/adder.vhd" 8 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adder:u1\|s\[0\] data_in GND " "Warning: Reduced register \"adder:u1\|s\[0\]\" with stuck data_in port to stuck value GND" {  } { { "adder.vhd" "" { Text "G:/eda/qdds/adder.vhd" 8 -1 0 } }  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "518 " "Info: Implemented 518 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "12 " "Info: Implemented 12 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "464 " "Info: Implemented 464 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "32 " "Info: Implemented 32 RAM segments" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jul 19 17:19:51 2008 " "Info: Processing ended: Sat Jul 19 17:19:51 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0}  } {  } 0}