dds.map.qmsg

多功能函数发生器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jul 19 17:19:41 2008 " "Info: Processing started: Sat Jul 19 17:19:41 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dds -c dds " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dds -c dds" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d_switch.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file d_switch.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 d_switch-behav " "Info: Found design unit 1: d_switch-behav" {  } { { "d_switch.vhd" "" { Text "G:/eda/qdds/d_switch.vhd" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 d_switch " "Info: Found entity 1: d_switch" {  } { { "d_switch.vhd" "" { Text "G:/eda/qdds/d_switch.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "dds.vhd 2 1 " "Info: Using design file dds.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dds-behav " "Info: Found design unit 1: dds-behav" {  } { { "dds.vhd" "" { Text "G:/eda/qdds/dds.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 dds " "Info: Found entity 1: dds" {  } { { "dds.vhd" "" { Text "G:/eda/qdds/dds.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "dds " "Info: Elaborating entity \"dds\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "adder.vhd 2 1 " "Info: Using design file adder.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 adder-behav " "Info: Found design unit 1: adder-behav" {  } { { "adder.vhd" "" { Text "G:/eda/qdds/adder.vhd" 10 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 adder " "Info: Found entity 1: adder" {  } { { "adder.vhd" "" { Text "G:/eda/qdds/adder.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "adder adder:u1 " "Info: Elaborating entity \"adder\" for hierarchy \"adder:u1\"" {  } { { "dds.vhd" "u1" { Text "G:/eda/qdds/dds.vhd" 62 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "d_switch d_switch:u2 " "Info: Elaborating entity \"d_switch\" for hierarchy \"d_switch:u2\"" {  } { { "dds.vhd" "u2" { Text "G:/eda/qdds/dds.vhd" 63 -1 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sw_in0 d_switch.vhd(13) " "Warning: VHDL Process Statement warning at d_switch.vhd(13): signal \"sw_in0\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "d_switch.vhd" "" { Text "G:/eda/qdds/d_switch.vhd" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sw_in1 d_switch.vhd(14) " "Warning: VHDL Process Statement warning at d_switch.vhd(14): signal \"sw_in1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "d_switch.vhd" "" { Text "G:/eda/qdds/d_switch.vhd" 14 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sw_in2 d_switch.vhd(15) " "Warning: VHDL Process Statement warning at d_switch.vhd(15): signal \"sw_in2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "d_switch.vhd" "" { Text "G:/eda/qdds/d_switch.vhd" 15 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sw_in3 d_switch.vhd(16) " "Warning: VHDL Process Statement warning at d_switch.vhd(16): signal \"sw_in3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "d_switch.vhd" "" { Text "G:/eda/qdds/d_switch.vhd" 16 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "d_switch.vhd(17) " "Info: VHDL Case Statement information at d_switch.vhd(17): OTHERS choice is never selected" {  } { { "d_switch.vhd" "" { Text "G:/eda/qdds/d_switch.vhd" 17 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "data_v.vhd 2 1 " "Info: Using design file data_v.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 data_v-SYN " "Info: Found design unit 1: data_v-SYN" {  } { { "data_v.vhd" "" { Text "G:/eda/qdds/data_v.vhd" 49 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 data_v " "Info: Found entity 1: data_v" {  } { { "data_v.vhd" "" { Text "G:/eda/qdds/data_v.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_v data_v:u31 " "Info: Elaborating entity \"data_v\" for hierarchy \"data_v:u31\"" {  } { { "dds.vhd" "u31" { Text "G:/eda/qdds/dds.vhd" 65 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus50/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus50/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram data_v:u31\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"data_v:u31\|altsyncram:altsyncram_component\"" {  } { { "data_v.vhd" "altsyncram_component" { Text "G:/eda/qdds/data_v.vhd" 80 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_8it.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_8it.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_8it " "Info: Found entity 1: altsyncram_8it" {  } { { "db/altsyncram_8it.tdf" "" { Text "G:/eda/qdds/db/altsyncram_8it.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_8it data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated " "Info: Elaborating entity \"altsyncram_8it\" for hierarchy \"data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/program files/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_iab2.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_iab2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_iab2 " "Info: Found entity 1: altsyncram_iab2" {  } { { "db/altsyncram_iab2.tdf" "" { Text "G:/eda/qdds/db/altsyncram_iab2.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_iab2 data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|altsyncram_iab2:altsyncram1 " "Info: Elaborating entity \"altsyncram_iab2\" for hierarchy \"data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|altsyncram_iab2:altsyncram1\"" {  } { { "db/altsyncram_8it.tdf" "altsyncram1" { Text "G:/eda/qdds/db/altsyncram_8it.tdf" 34 2 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file d:/program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_mod_ram_rom_pack " "Info: Found design unit 1: sld_mod_ram_rom_pack" {  } { { "sld_mod_ram_rom.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd" 4 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_mod_ram_rom-rtl " "Info: Found design unit 2: sld_mod_ram_rom-rtl" {  } { { "sld_mod_ram_rom.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd" 72 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_mod_ram_rom " "Info: Found entity 1: sld_mod_ram_rom" {  } { { "sld_mod_ram_rom.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd" 16 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_mod_ram_rom data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Elaborating entity \"sld_mod_ram_rom\" for hierarchy \"data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2\"" {  } { { "db/altsyncram_8it.tdf" "mgl_prim2" { Text "G:/eda/qdds/db/altsyncram_8it.tdf" 35 2 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file d:/program files/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_rom_sr-INFO_REG " "Info: Found design unit 1: sld_rom_sr-INFO_REG" {  } { { "sld_rom_sr.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 27 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_rom_sr " "Info: Found entity 1: sld_rom_sr" {  } { { "sld_rom_sr.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_rom_sr data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr " "Info: Elaborating entity \"sld_rom_sr\" for hierarchy \"data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr\"" {  } { { "sld_mod_ram_rom.vhd" "\\ram_rom_logic_gen:name_gen:info_rom_sr" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd" 650 -1 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "data_f.vhd 2 1 " "Info: Using design file data_f.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 data_f-SYN " "Info: Found design unit 1: data_f-SYN" {  } { { "data_f.vhd" "" { Text "G:/eda/qdds/data_f.vhd" 49 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 data_f " "Info: Found entity 1: data_f" {  } { { "data_f.vhd" "" { Text "G:/eda/qdds/data_f.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_f data_f:u32 " "Info: Elaborating entity \"data_f\" for hierarchy \"data_f:u32\"" {  } { { "dds.vhd" "u32" { Text "G:/eda/qdds/dds.vhd" 66 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram data_f:u32\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"data_f:u32\|altsyncram:altsyncram_component\"" {  } { { "data_f.vhd" "altsyncram_component" { Text "G:/eda/qdds/data_f.vhd" 80 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_pht.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_pht.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_pht " "Info: Found entity 1: altsyncram_pht" {  } { { "db/altsyncram_pht.tdf" "" { Text "G:/eda/qdds/db/altsyncram_pht.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_pht data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated " "Info: Elaborating entity \"altsyncram_pht\" for hierarchy \"data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/program files/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}