dds.tan.qmsg

多功能函数发生器

{ "Info" "ITDB_TH_RESULT" "data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[7\] altera_internal_jtag altera_internal_jtag~TCKUTAP 3.285 ns register " "Info: th for register \"data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[7\]\" (data pin = \"altera_internal_jtag\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 3.285 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.273 ns + Longest register " "Info: + Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.273 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 346 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 346; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.562 ns) + CELL(0.711 ns) 5.273 ns data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[7\] 2 REG LC_X15_Y6_N7 3 " "Info: 2: + IC(4.562 ns) + CELL(0.711 ns) = 5.273 ns; Loc. = LC_X15_Y6_N7; Fanout = 3; REG Node = 'data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[7\]'" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "5.273 ns" { altera_internal_jtag~TCKUTAP data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7] } "NODE_NAME" } "" } } { "sld_mod_ram_rom.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd" 160 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.48 % " "Info: Total cell delay = 0.711 ns ( 13.48 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.562 ns 86.52 % " "Info: Total interconnect delay = 4.562 ns ( 86.52 % )" {  } {  } 0}  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "5.273 ns" { altera_internal_jtag~TCKUTAP data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "5.273 ns" { altera_internal_jtag~TCKUTAP data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7] } { 0.000ns 4.562ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "sld_mod_ram_rom.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd" 160 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.003 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.003 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag 1 PIN JTAG_X1_Y6_N1 25 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 25; PIN Node = 'altera_internal_jtag'" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { altera_internal_jtag } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.888 ns) + CELL(0.115 ns) 2.003 ns data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[7\] 2 REG LC_X15_Y6_N7 3 " "Info: 2: + IC(1.888 ns) + CELL(0.115 ns) = 2.003 ns; Loc. = LC_X15_Y6_N7; Fanout = 3; REG Node = 'data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[7\]'" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "2.003 ns" { altera_internal_jtag data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7] } "NODE_NAME" } "" } } { "sld_mod_ram_rom.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd" 160 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns 5.74 % " "Info: Total cell delay = 0.115 ns ( 5.74 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.888 ns 94.26 % " "Info: Total interconnect delay = 1.888 ns ( 94.26 % )" {  } {  } 0}  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "2.003 ns" { altera_internal_jtag data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.003 ns" { altera_internal_jtag data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7] } { 0.000ns 1.888ns } { 0.000ns 0.115ns } } }  } 0}  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "5.273 ns" { altera_internal_jtag~TCKUTAP data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "5.273 ns" { altera_internal_jtag~TCKUTAP data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7] } { 0.000ns 4.562ns } { 0.000ns 0.711ns } } } { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "2.003 ns" { altera_internal_jtag data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.003 ns" { altera_internal_jtag data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7] } { 0.000ns 1.888ns } { 0.000ns 0.115ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jul 19 17:20:05 2008 " "Info: Processing ended: Sat Jul 19 17:20:05 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}