📄 dds.tan.qmsg
字号:
{ "Info" "ITDB_TSU_RESULT" "adder:u1\|s\[14\] f_c\[2\] clk 6.871 ns register " "Info: tsu for register \"adder:u1\|s\[14\]\" (data pin = \"f_c\[2\]\", clock pin = \"clk\") is 6.871 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.574 ns + Longest pin register " "Info: + Longest pin to register delay is 9.574 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns f_c\[2\] 1 PIN PIN_3 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_3; Fanout = 3; PIN Node = 'f_c\[2\]'" { } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { f_c[2] } "NODE_NAME" } "" } } { "dds.vhd" "" { Text "G:/eda/qdds/dds.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.057 ns) + CELL(0.575 ns) 8.101 ns adder:u1\|s\[4\]~145COUT1_158 2 COMB LC_X11_Y9_N5 2 " "Info: 2: + IC(6.057 ns) + CELL(0.575 ns) = 8.101 ns; Loc. = LC_X11_Y9_N5; Fanout = 2; COMB Node = 'adder:u1\|s\[4\]~145COUT1_158'" { } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "6.632 ns" { f_c[2] adder:u1|s[4]~145COUT1_158 } "NODE_NAME" } "" } } { "adder.vhd" "" { Text "G:/eda/qdds/adder.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 8.181 ns adder:u1\|s\[5\]~141COUT1_159 3 COMB LC_X11_Y9_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 8.181 ns; Loc. = LC_X11_Y9_N6; Fanout = 2; COMB Node = 'adder:u1\|s\[5\]~141COUT1_159'" { } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "0.080 ns" { adder:u1|s[4]~145COUT1_158 adder:u1|s[5]~141COUT1_159 } "NODE_NAME" } "" } } { "adder.vhd" "" { Text "G:/eda/qdds/adder.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 8.261 ns adder:u1\|s\[6\]~137COUT1_160 4 COMB LC_X11_Y9_N7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 8.261 ns; Loc. = LC_X11_Y9_N7; Fanout = 2; COMB Node = 'adder:u1\|s\[6\]~137COUT1_160'" { } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "0.080 ns" { adder:u1|s[5]~141COUT1_159 adder:u1|s[6]~137COUT1_160 } "NODE_NAME" } "" } } { "adder.vhd" "" { Text "G:/eda/qdds/adder.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 8.341 ns adder:u1\|s\[7\]~133COUT1_161 5 COMB LC_X11_Y9_N8 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 8.341 ns; Loc. = LC_X11_Y9_N8; Fanout = 2; COMB Node = 'adder:u1\|s\[7\]~133COUT1_161'" { } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "0.080 ns" { adder:u1|s[6]~137COUT1_160 adder:u1|s[7]~133COUT1_161 } "NODE_NAME" } "" } } { "adder.vhd" "" { Text "G:/eda/qdds/adder.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 8.599 ns adder:u1\|s\[8\]~101 6 COMB LC_X11_Y9_N9 6 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 8.599 ns; Loc. = LC_X11_Y9_N9; Fanout = 6; COMB Node = 'adder:u1\|s\[8\]~101'" { } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "0.258 ns" { adder:u1|s[7]~133COUT1_161 adder:u1|s[8]~101 } "NODE_NAME" } "" } } { "adder.vhd" "" { Text "G:/eda/qdds/adder.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 8.735 ns adder:u1\|s\[13\]~121 7 COMB LC_X11_Y8_N4 2 " "Info: 7: + IC(0.000 ns) + CELL(0.136 ns) = 8.735 ns; Loc. = LC_X11_Y8_N4; Fanout = 2; COMB Node = 'adder:u1\|s\[13\]~121'" { } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "0.136 ns" { adder:u1|s[8]~101 adder:u1|s[13]~121 } "NODE_NAME" } "" } } { "adder.vhd" "" { Text "G:/eda/qdds/adder.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 9.574 ns adder:u1\|s\[14\] 8 REG LC_X11_Y8_N5 7 " "Info: 8: + IC(0.000 ns) + CELL(0.839 ns) = 9.574 ns; Loc. = LC_X11_Y8_N5; Fanout = 7; REG Node = 'adder:u1\|s\[14\]'" { } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "0.839 ns" { adder:u1|s[13]~121 adder:u1|s[14] } "NODE_NAME" } "" } } { "adder.vhd" "" { Text "G:/eda/qdds/adder.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.517 ns 36.73 % " "Info: Total cell delay = 3.517 ns ( 36.73 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.057 ns 63.27 % " "Info: Total interconnect delay = 6.057 ns ( 63.27 % )" { } { } 0} } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "9.574 ns" { f_c[2] adder:u1|s[4]~145COUT1_158 adder:u1|s[5]~141COUT1_159 adder:u1|s[6]~137COUT1_160 adder:u1|s[7]~133COUT1_161 adder:u1|s[8]~101 adder:u1|s[13]~121 adder:u1|s[14] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "9.574 ns" { f_c[2] f_c[2]~out0 adder:u1|s[4]~145COUT1_158 adder:u1|s[5]~141COUT1_159 adder:u1|s[6]~137COUT1_160 adder:u1|s[7]~133COUT1_161 adder:u1|s[8]~101 adder:u1|s[13]~121 adder:u1|s[14] } { 0.000ns 0.000ns 6.057ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.469ns 0.575ns 0.080ns 0.080ns 0.080ns 0.258ns 0.136ns 0.839ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "adder.vhd" "" { Text "G:/eda/qdds/adder.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.740 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 114 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 114; CLK Node = 'clk'" { } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { clk } "NODE_NAME" } "" } } { "dds.vhd" "" { Text "G:/eda/qdds/dds.vhd" 4 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.711 ns) 2.740 ns adder:u1\|s\[14\] 2 REG LC_X11_Y8_N5 7 " "Info: 2: + IC(0.560 ns) + CELL(0.711 ns) = 2.740 ns; Loc. = LC_X11_Y8_N5; Fanout = 7; REG Node = 'adder:u1\|s\[14\]'" { } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "1.271 ns" { clk adder:u1|s[14] } "NODE_NAME" } "" } } { "adder.vhd" "" { Text "G:/eda/qdds/adder.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.56 % " "Info: Total cell delay = 2.180 ns ( 79.56 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.560 ns 20.44 % " "Info: Total interconnect delay = 0.560 ns ( 20.44 % )" { } { } 0} } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "2.740 ns" { clk adder:u1|s[14] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.740 ns" { clk clk~out0 adder:u1|s[14] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "9.574 ns" { f_c[2] adder:u1|s[4]~145COUT1_158 adder:u1|s[5]~141COUT1_159 adder:u1|s[6]~137COUT1_160 adder:u1|s[7]~133COUT1_161 adder:u1|s[8]~101 adder:u1|s[13]~121 adder:u1|s[14] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "9.574 ns" { f_c[2] f_c[2]~out0 adder:u1|s[4]~145COUT1_158 adder:u1|s[5]~141COUT1_159 adder:u1|s[6]~137COUT1_160 adder:u1|s[7]~133COUT1_161 adder:u1|s[8]~101 adder:u1|s[13]~121 adder:u1|s[14] } { 0.000ns 0.000ns 6.057ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.469ns 0.575ns 0.080ns 0.080ns 0.080ns 0.258ns 0.136ns 0.839ns } } } { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "2.740 ns" { clk adder:u1|s[14] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.740 ns" { clk clk~out0 adder:u1|s[14] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk s_out\[3\] data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|altsyncram_2ab2:altsyncram1\|ram_block3a0~porta_address_reg0 15.975 ns memory " "Info: tco from clock \"clk\" to destination pin \"s_out\[3\]\" through memory \"data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|altsyncram_2ab2:altsyncram1\|ram_block3a0~porta_address_reg0\" is 15.975 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.792 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to source memory is 2.792 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 114 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 114; CLK Node = 'clk'" { } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { clk } "NODE_NAME" } "" } } { "dds.vhd" "" { Text "G:/eda/qdds/dds.vhd" 4 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.722 ns) 2.792 ns data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|altsyncram_2ab2:altsyncram1\|ram_block3a0~porta_address_reg0 2 MEM M4K_X13_Y9 8 " "Info: 2: + IC(0.601 ns) + CELL(0.722 ns) = 2.792 ns; Loc. = M4K_X13_Y9; Fanout = 8; MEM Node = 'data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|altsyncram_2ab2:altsyncram1\|ram_block3a0~porta_address_reg0'" { } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "1.323 ns" { clk data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_2ab2.tdf" "" { Text "G:/eda/qdds/db/altsyncram_2ab2.tdf" 46 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns 78.47 % " "Info: Total cell delay = 2.191 ns ( 78.47 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns 21.53 % " "Info: Total interconnect delay = 0.601 ns ( 21.53 % )" { } { } 0} } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "2.792 ns" { clk data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.792 ns" { clk clk~out0 data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1|ram_block3a0~porta_address_reg0 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.722ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" { } { { "db/altsyncram_2ab2.tdf" "" { Text "G:/eda/qdds/db/altsyncram_2ab2.tdf" 46 2 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.533 ns + Longest memory pin " "Info: + Longest memory to pin delay is 12.533 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|altsyncram_2ab2:altsyncram1\|ram_block3a0~porta_address_reg0 1 MEM M4K_X13_Y9 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y9; Fanout = 8; MEM Node = 'data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|altsyncram_2ab2:altsyncram1\|ram_block3a0~porta_address_reg0'" { } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_2ab2.tdf" "" { Text "G:/eda/qdds/db/altsyncram_2ab2.tdf" 46 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.308 ns) 4.308 ns data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|altsyncram_2ab2:altsyncram1\|q_a\[3\] 2 MEM M4K_X13_Y9 1 " "Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X13_Y9; Fanout = 1; MEM Node = 'data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|altsyncram_2ab2:altsyncram1\|q_a\[3\]'" { } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "4.308 ns" { data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1|ram_block3a0~porta_address_reg0 data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1|q_a[3] } "NODE_NAME" } "" } } { "db/altsyncram_2ab2.tdf" "" { Text "G:/eda/qdds/db/altsyncram_2ab2.tdf" 41 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.935 ns) + CELL(0.292 ns) 6.535 ns d_switch:u2\|sw_out\[3\]~114 3 COMB LC_X15_Y5_N1 1 " "Info: 3: + IC(1.935 ns) + CELL(0.292 ns) = 6.535 ns; Loc. = LC_X15_Y5_N1; Fanout = 1; COMB Node = 'd_switch:u2\|sw_out\[3\]~114'" { } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "2.227 ns" { data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1|q_a[3] d_switch:u2|sw_out[3]~114 } "NODE_NAME" } "" } } { "d_switch.vhd" "" { Text "G:/eda/qdds/d_switch.vhd" 4 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.242 ns) + CELL(0.590 ns) 8.367 ns d_switch:u2\|sw_out\[3\]~115 4 COMB LC_X15_Y4_N2 1 " "Info: 4: + IC(1.242 ns) + CELL(0.590 ns) = 8.367 ns; Loc. = LC_X15_Y4_N2; Fanout = 1; COMB Node = 'd_switch:u2\|sw_out\[3\]~115'" { } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "1.832 ns" { d_switch:u2|sw_out[3]~114 d_switch:u2|sw_out[3]~115 } "NODE_NAME" } "" } } { "d_switch.vhd" "" { Text "G:/eda/qdds/d_switch.vhd" 4 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.058 ns) + CELL(2.108 ns) 12.533 ns s_out\[3\] 5 PIN PIN_68 0 " "Info: 5: + IC(2.058 ns) + CELL(2.108 ns) = 12.533 ns; Loc. = PIN_68; Fanout = 0; PIN Node = 's_out\[3\]'" { } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "4.166 ns" { d_switch:u2|sw_out[3]~115 s_out[3] } "NODE_NAME" } "" } } { "dds.vhd" "" { Text "G:/eda/qdds/dds.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.298 ns 58.23 % " "Info: Total cell delay = 7.298 ns ( 58.23 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.235 ns 41.77 % " "Info: Total interconnect delay = 5.235 ns ( 41.77 % )" { } { } 0} } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "12.533 ns" { data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1|ram_block3a0~porta_address_reg0 data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1|q_a[3] d_switch:u2|sw_out[3]~114 d_switch:u2|sw_out[3]~115 s_out[3] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "12.533 ns" { data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1|ram_block3a0~porta_address_reg0 data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1|q_a[3] d_switch:u2|sw_out[3]~114 d_switch:u2|sw_out[3]~115 s_out[3] } { 0.000ns 0.000ns 1.935ns 1.242ns 2.058ns } { 0.000ns 4.308ns 0.292ns 0.590ns 2.108ns } } } } 0} } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "2.792 ns" { clk data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.792 ns" { clk clk~out0 data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1|ram_block3a0~porta_address_reg0 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.722ns } } } { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "12.533 ns" { data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1|ram_block3a0~porta_address_reg0 data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1|q_a[3] d_switch:u2|sw_out[3]~114 d_switch:u2|sw_out[3]~115 s_out[3] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "12.533 ns" { data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1|ram_block3a0~porta_address_reg0 data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1|q_a[3] d_switch:u2|sw_out[3]~114 d_switch:u2|sw_out[3]~115 s_out[3] } { 0.000ns 0.000ns 1.935ns 1.242ns 2.058ns } { 0.000ns 4.308ns 0.292ns 0.590ns 2.108ns } } } } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "switch\[1\] s_out\[3\] 15.176 ns Longest " "Info: Longest tpd from source pin \"switch\[1\]\" to destination pin \"s_out\[3\]\" is 15.176 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns switch\[1\] 1 PIN PIN_10 12 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_10; Fanout = 12; PIN Node = 'switch\[1\]'" { } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { switch[1] } "NODE_NAME" } "" } } { "dds.vhd" "" { Text "G:/eda/qdds/dds.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(7.119 ns) + CELL(0.590 ns) 9.178 ns d_switch:u2\|sw_out\[3\]~114 2 COMB LC_X15_Y5_N1 1 " "Info: 2: + IC(7.119 ns) + CELL(0.590 ns) = 9.178 ns; Loc. = LC_X15_Y5_N1; Fanout = 1; COMB Node = 'd_switch:u2\|sw_out\[3\]~114'" { } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "7.709 ns" { switch[1] d_switch:u2|sw_out[3]~114 } "NODE_NAME" } "" } } { "d_switch.vhd" "" { Text "G:/eda/qdds/d_switch.vhd" 4 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.242 ns) + CELL(0.590 ns) 11.010 ns d_switch:u2\|sw_out\[3\]~115 3 COMB LC_X15_Y4_N2 1 " "Info: 3: + IC(1.242 ns) + CELL(0.590 ns) = 11.010 ns; Loc. = LC_X15_Y4_N2; Fanout = 1; COMB Node = 'd_switch:u2\|sw_out\[3\]~115'" { } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "1.832 ns" { d_switch:u2|sw_out[3]~114 d_switch:u2|sw_out[3]~115 } "NODE_NAME" } "" } } { "d_switch.vhd" "" { Text "G:/eda/qdds/d_switch.vhd" 4 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.058 ns) + CELL(2.108 ns) 15.176 ns s_out\[3\] 4 PIN PIN_68 0 " "Info: 4: + IC(2.058 ns) + CELL(2.108 ns) = 15.176 ns; Loc. = PIN_68; Fanout = 0; PIN Node = 's_out\[3\]'" { } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "4.166 ns" { d_switch:u2|sw_out[3]~115 s_out[3] } "NODE_NAME" } "" } } { "dds.vhd" "" { Text "G:/eda/qdds/dds.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.757 ns 31.35 % " "Info: Total cell delay = 4.757 ns ( 31.35 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.419 ns 68.65 % " "Info: Total interconnect delay = 10.419 ns ( 68.65 % )" { } { } 0} } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "15.176 ns" { switch[1] d_switch:u2|sw_out[3]~114 d_switch:u2|sw_out[3]~115 s_out[3] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "15.176 ns" { switch[1] switch[1]~out0 d_switch:u2|sw_out[3]~114 d_switch:u2|sw_out[3]~115 s_out[3] } { 0.000ns 0.000ns 7.119ns 1.242ns 2.058ns } { 0.000ns 1.469ns 0.590ns 0.590ns 2.108ns } } } } 0}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -