dds.tan.qmsg

多功能函数发生器

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "dds.vhd" "" { Text "G:/eda/qdds/dds.vhd" 4 -1 0 } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk memory data_sin:u34\|altsyncram:altsyncram_component\|altsyncram_rot:auto_generated\|altsyncram_6hb2:altsyncram1\|ram_block3a0~porta_datain_reg7 memory data_sin:u34\|altsyncram:altsyncram_component\|altsyncram_rot:auto_generated\|altsyncram_6hb2:altsyncram1\|ram_block3a0~porta_memory_reg7 197.01 MHz 5.076 ns Internal " "Info: Clock \"clk\" has Internal fmax of 197.01 MHz between source memory \"data_sin:u34\|altsyncram:altsyncram_component\|altsyncram_rot:auto_generated\|altsyncram_6hb2:altsyncram1\|ram_block3a0~porta_datain_reg7\" and destination memory \"data_sin:u34\|altsyncram:altsyncram_component\|altsyncram_rot:auto_generated\|altsyncram_6hb2:altsyncram1\|ram_block3a0~porta_memory_reg7\" (period= 5.076 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns + Longest memory memory " "Info: + Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data_sin:u34\|altsyncram:altsyncram_component\|altsyncram_rot:auto_generated\|altsyncram_6hb2:altsyncram1\|ram_block3a0~porta_datain_reg7 1 MEM M4K_X13_Y5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y5; Fanout = 1; MEM Node = 'data_sin:u34\|altsyncram:altsyncram_component\|altsyncram_rot:auto_generated\|altsyncram_6hb2:altsyncram1\|ram_block3a0~porta_datain_reg7'" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|altsyncram_6hb2:altsyncram1|ram_block3a0~porta_datain_reg7 } "NODE_NAME" } "" } } { "db/altsyncram_6hb2.tdf" "" { Text "G:/eda/qdds/db/altsyncram_6hb2.tdf" 46 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns data_sin:u34\|altsyncram:altsyncram_component\|altsyncram_rot:auto_generated\|altsyncram_6hb2:altsyncram1\|ram_block3a0~porta_memory_reg7 2 MEM M4K_X13_Y5 0 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X13_Y5; Fanout = 0; MEM Node = 'data_sin:u34\|altsyncram:altsyncram_component\|altsyncram_rot:auto_generated\|altsyncram_6hb2:altsyncram1\|ram_block3a0~porta_memory_reg7'" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "4.319 ns" { data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|altsyncram_6hb2:altsyncram1|ram_block3a0~porta_datain_reg7 data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|altsyncram_6hb2:altsyncram1|ram_block3a0~porta_memory_reg7 } "NODE_NAME" } "" } } { "db/altsyncram_6hb2.tdf" "" { Text "G:/eda/qdds/db/altsyncram_6hb2.tdf" 46 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns 100.00 % " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0}  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "4.319 ns" { data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|altsyncram_6hb2:altsyncram1|ram_block3a0~porta_datain_reg7 data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|altsyncram_6hb2:altsyncram1|ram_block3a0~porta_memory_reg7 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "4.319 ns" { data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|altsyncram_6hb2:altsyncram1|ram_block3a0~porta_datain_reg7 data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|altsyncram_6hb2:altsyncram1|ram_block3a0~porta_memory_reg7 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.014 ns - Smallest " "Info: - Smallest clock skew is -0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.740 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk\" to destination memory is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 114 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 114; CLK Node = 'clk'" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { clk } "NODE_NAME" } "" } } { "dds.vhd" "" { Text "G:/eda/qdds/dds.vhd" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.708 ns) 2.740 ns data_sin:u34\|altsyncram:altsyncram_component\|altsyncram_rot:auto_generated\|altsyncram_6hb2:altsyncram1\|ram_block3a0~porta_memory_reg7 2 MEM M4K_X13_Y5 0 " "Info: 2: + IC(0.563 ns) + CELL(0.708 ns) = 2.740 ns; Loc. = M4K_X13_Y5; Fanout = 0; MEM Node = 'data_sin:u34\|altsyncram:altsyncram_component\|altsyncram_rot:auto_generated\|altsyncram_6hb2:altsyncram1\|ram_block3a0~porta_memory_reg7'" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "1.271 ns" { clk data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|altsyncram_6hb2:altsyncram1|ram_block3a0~porta_memory_reg7 } "NODE_NAME" } "" } } { "db/altsyncram_6hb2.tdf" "" { Text "G:/eda/qdds/db/altsyncram_6hb2.tdf" 46 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.177 ns 79.45 % " "Info: Total cell delay = 2.177 ns ( 79.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns 20.55 % " "Info: Total interconnect delay = 0.563 ns ( 20.55 % )" {  } {  } 0}  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "2.740 ns" { clk data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|altsyncram_6hb2:altsyncram1|ram_block3a0~porta_memory_reg7 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.740 ns" { clk clk~out0 data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|altsyncram_6hb2:altsyncram1|ram_block3a0~porta_memory_reg7 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.708ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.754 ns - Longest memory " "Info: - Longest clock path from clock \"clk\" to source memory is 2.754 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 114 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 114; CLK Node = 'clk'" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { clk } "NODE_NAME" } "" } } { "dds.vhd" "" { Text "G:/eda/qdds/dds.vhd" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.722 ns) 2.754 ns data_sin:u34\|altsyncram:altsyncram_component\|altsyncram_rot:auto_generated\|altsyncram_6hb2:altsyncram1\|ram_block3a0~porta_datain_reg7 2 MEM M4K_X13_Y5 1 " "Info: 2: + IC(0.563 ns) + CELL(0.722 ns) = 2.754 ns; Loc. = M4K_X13_Y5; Fanout = 1; MEM Node = 'data_sin:u34\|altsyncram:altsyncram_component\|altsyncram_rot:auto_generated\|altsyncram_6hb2:altsyncram1\|ram_block3a0~porta_datain_reg7'" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "1.285 ns" { clk data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|altsyncram_6hb2:altsyncram1|ram_block3a0~porta_datain_reg7 } "NODE_NAME" } "" } } { "db/altsyncram_6hb2.tdf" "" { Text "G:/eda/qdds/db/altsyncram_6hb2.tdf" 46 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns 79.56 % " "Info: Total cell delay = 2.191 ns ( 79.56 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns 20.44 % " "Info: Total interconnect delay = 0.563 ns ( 20.44 % )" {  } {  } 0}  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "2.754 ns" { clk data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|altsyncram_6hb2:altsyncram1|ram_block3a0~porta_datain_reg7 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.754 ns" { clk clk~out0 data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|altsyncram_6hb2:altsyncram1|ram_block3a0~porta_datain_reg7 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.722ns } } }  } 0}  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "2.740 ns" { clk data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|altsyncram_6hb2:altsyncram1|ram_block3a0~porta_memory_reg7 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.740 ns" { clk clk~out0 data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|altsyncram_6hb2:altsyncram1|ram_block3a0~porta_memory_reg7 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.708ns } } } { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "2.754 ns" { clk data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|altsyncram_6hb2:altsyncram1|ram_block3a0~porta_datain_reg7 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.754 ns" { clk clk~out0 data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|altsyncram_6hb2:altsyncram1|ram_block3a0~porta_datain_reg7 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.722ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_6hb2.tdf" "" { Text "G:/eda/qdds/db/altsyncram_6hb2.tdf" 46 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_6hb2.tdf" "" { Text "G:/eda/qdds/db/altsyncram_6hb2.tdf" 46 2 0 } }  } 0}  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "4.319 ns" { data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|altsyncram_6hb2:altsyncram1|ram_block3a0~porta_datain_reg7 data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|altsyncram_6hb2:altsyncram1|ram_block3a0~porta_memory_reg7 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "4.319 ns" { data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|altsyncram_6hb2:altsyncram1|ram_block3a0~porta_datain_reg7 data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|altsyncram_6hb2:altsyncram1|ram_block3a0~porta_memory_reg7 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } } { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "2.740 ns" { clk data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|altsyncram_6hb2:altsyncram1|ram_block3a0~porta_memory_reg7 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.740 ns" { clk clk~out0 data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|altsyncram_6hb2:altsyncram1|ram_block3a0~porta_memory_reg7 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.708ns } } } { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "2.754 ns" { clk data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|altsyncram_6hb2:altsyncram1|ram_block3a0~porta_datain_reg7 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.754 ns" { clk clk~out0 data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|altsyncram_6hb2:altsyncram1|ram_block3a0~porta_datain_reg7 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.722ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:4:IRF\|Q\[2\] register sld_hub:sld_hub_inst\|hub_tdo 85.69 MHz 11.67 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 85.69 MHz between source register \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:4:IRF\|Q\[2\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 11.67 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.574 ns + Longest register register " "Info: + Longest register to register delay is 5.574 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:4:IRF\|Q\[2\] 1 REG LC_X18_Y6_N5 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y6_N5; Fanout = 5; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:4:IRF\|Q\[2\]'" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:4:IRF|Q[2] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.537 ns) + CELL(0.442 ns) 0.979 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:4:IRF\|Q\[1\]~47 2 COMB LC_X18_Y6_N2 2 " "Info: 2: + IC(0.537 ns) + CELL(0.442 ns) = 0.979 ns; Loc. = LC_X18_Y6_N2; Fanout = 2; COMB Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:4:IRF\|Q\[1\]~47'" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "0.979 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:4:IRF|Q[2] sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:4:IRF|Q[1]~47 } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.455 ns) + CELL(0.590 ns) 2.024 ns sld_hub:sld_hub_inst\|hub_tdo~1068 3 COMB LC_X18_Y6_N4 1 " "Info: 3: + IC(0.455 ns) + CELL(0.590 ns) = 2.024 ns; Loc. = LC_X18_Y6_N4; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~1068'" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "1.045 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:4:IRF|Q[1]~47 sld_hub:sld_hub_inst|hub_tdo~1068 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.072 ns) + CELL(0.442 ns) 3.538 ns sld_hub:sld_hub_inst\|hub_tdo~1069 4 COMB LC_X20_Y6_N6 1 " "Info: 4: + IC(1.072 ns) + CELL(0.442 ns) = 3.538 ns; Loc. = LC_X20_Y6_N6; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~1069'" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "1.514 ns" { sld_hub:sld_hub_inst|hub_tdo~1068 sld_hub:sld_hub_inst|hub_tdo~1069 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.433 ns) + CELL(0.590 ns) 4.561 ns sld_hub:sld_hub_inst\|hub_tdo~1073 5 COMB LC_X20_Y6_N5 1 " "Info: 5: + IC(0.433 ns) + CELL(0.590 ns) = 4.561 ns; Loc. = LC_X20_Y6_N5; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~1073'" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "1.023 ns" { sld_hub:sld_hub_inst|hub_tdo~1069 sld_hub:sld_hub_inst|hub_tdo~1073 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.406 ns) + CELL(0.607 ns) 5.574 ns sld_hub:sld_hub_inst\|hub_tdo 6 REG LC_X20_Y6_N4 0 " "Info: 6: + IC(0.406 ns) + CELL(0.607 ns) = 5.574 ns; Loc. = LC_X20_Y6_N4; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "1.013 ns" { sld_hub:sld_hub_inst|hub_tdo~1073 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.671 ns 47.92 % " "Info: Total cell delay = 2.671 ns ( 47.92 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.903 ns 52.08 % " "Info: Total interconnect delay = 2.903 ns ( 52.08 % )" {  } {  } 0}  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "5.574 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:4:IRF|Q[2] sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:4:IRF|Q[1]~47 sld_hub:sld_hub_inst|hub_tdo~1068 sld_hub:sld_hub_inst|hub_tdo~1069 sld_hub:sld_hub_inst|hub_tdo~1073 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "5.574 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:4:IRF|Q[2] sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:4:IRF|Q[1]~47 sld_hub:sld_hub_inst|hub_tdo~1068 sld_hub:sld_hub_inst|hub_tdo~1069 sld_hub:sld_hub_inst|hub_tdo~1073 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 0.537ns 0.455ns 1.072ns 0.433ns 0.406ns } { 0.000ns 0.442ns 0.590ns 0.442ns 0.590ns 0.607ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.273 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.273 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 346 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 346; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.562 ns) + CELL(0.711 ns) 5.273 ns sld_hub:sld_hub_inst\|hub_tdo 2 REG LC_X20_Y6_N4 0 " "Info: 2: + IC(4.562 ns) + CELL(0.711 ns) = 5.273 ns; Loc. = LC_X20_Y6_N4; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "5.273 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.48 % " "Info: Total cell delay = 0.711 ns ( 13.48 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.562 ns 86.52 % " "Info: Total interconnect delay = 4.562 ns ( 86.52 % )" {  } {  } 0}  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "5.273 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "5.273 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.562ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.273 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.273 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 346 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 346; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.562 ns) + CELL(0.711 ns) 5.273 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:4:IRF\|Q\[2\] 2 REG LC_X18_Y6_N5 5 " "Info: 2: + IC(4.562 ns) + CELL(0.711 ns) = 5.273 ns; Loc. = LC_X18_Y6_N5; Fanout = 5; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:4:IRF\|Q\[2\]'" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "5.273 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:4:IRF|Q[2] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.48 % " "Info: Total cell delay = 0.711 ns ( 13.48 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.562 ns 86.52 % " "Info: Total interconnect delay = 4.562 ns ( 86.52 % )" {  } {  } 0}  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "5.273 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:4:IRF|Q[2] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "5.273 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:4:IRF|Q[2] } { 0.000ns 4.562ns } { 0.000ns 0.711ns } } }  } 0}  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "5.273 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "5.273 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.562ns } { 0.000ns 0.711ns } } } { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "5.273 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:4:IRF|Q[2] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "5.273 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:4:IRF|Q[2] } { 0.000ns 4.562ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "sld_dffex.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "sld_dffex.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0}  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "5.574 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:4:IRF|Q[2] sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:4:IRF|Q[1]~47 sld_hub:sld_hub_inst|hub_tdo~1068 sld_hub:sld_hub_inst|hub_tdo~1069 sld_hub:sld_hub_inst|hub_tdo~1073 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "5.574 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:4:IRF|Q[2] sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:4:IRF|Q[1]~47 sld_hub:sld_hub_inst|hub_tdo~1068 sld_hub:sld_hub_inst|hub_tdo~1069 sld_hub:sld_hub_inst|hub_tdo~1073 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 0.537ns 0.455ns 1.072ns 0.433ns 0.406ns } { 0.000ns 0.442ns 0.590ns 0.442ns 0.590ns 0.607ns } } } { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "5.273 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "5.273 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.562ns } { 0.000ns 0.711ns } } } { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "5.273 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:4:IRF|Q[2] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "5.273 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:4:IRF|Q[2] } { 0.000ns 4.562ns } { 0.000ns 0.711ns } } }  } 0}