dds.fit.qmsg

多功能函数发生器

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "5 8 " "Info: Average interconnect usage is 5% of the available device resources. Peak interconnect usage is 8%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|sld_dffex:RESET\|Q\[0\] " "Info: Node sld_hub:sld_hub_inst\|sld_dffex:RESET\|Q\[0\] uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[3\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[3\] -- routed using non-global resources" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[3] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[3\]" } } } } { "sld_dffex.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "G:/eda/qdds/dds.fld" "" { Floorplan "G:/eda/qdds/dds.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] -- routed using non-global resources" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\]" } } } } { "sld_dffex.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "G:/eda/qdds/dds.fld" "" { Floorplan "G:/eda/qdds/dds.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } }  } 0}  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:RESET\|Q\[0\]" } } } } { "sld_dffex.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "G:/eda/qdds/dds.fld" "" { Floorplan "G:/eda/qdds/dds.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0] } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " "Info: Node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|jtag_debug_mode_usr0 " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|jtag_debug_mode_usr0 -- routed using non-global resources" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr0 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|jtag_debug_mode_usr0" } } } } { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 380 -1 0 } } { "G:/eda/qdds/dds.fld" "" { Floorplan "G:/eda/qdds/dds.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr0 } "NODE_NAME" } }  } 0}  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]" } } } } { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1014 -1 0 } } { "G:/eda/qdds/dds.fld" "" { Floorplan "G:/eda/qdds/dds.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[0\] " "Info: Node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[0\] uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[3\] " "Info: Port clear -- assigned as a global for destination node data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[3\] -- routed using non-global resources" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[3\]" } } } } { "sld_mod_ram_rom.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd" 177 -1 0 } } { "G:/eda/qdds/dds.fld" "" { Floorplan "G:/eda/qdds/dds.fld" "" "" { data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[0\] " "Info: Port clear -- assigned as a global for destination node data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[0\] -- routed using non-global resources" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[0\]" } } } } { "sld_mod_ram_rom.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd" 177 -1 0 } } { "G:/eda/qdds/dds.fld" "" { Floorplan "G:/eda/qdds/dds.fld" "" "" { data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[1\] " "Info: Port clear -- assigned as a global for destination node data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[1\] -- routed using non-global resources" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[1\]" } } } } { "sld_mod_ram_rom.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd" 177 -1 0 } } { "G:/eda/qdds/dds.fld" "" { Floorplan "G:/eda/qdds/dds.fld" "" "" { data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[2\] " "Info: Port clear -- assigned as a global for destination node data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[2\] -- routed using non-global resources" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[2\]" } } } } { "sld_mod_ram_rom.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd" 177 -1 0 } } { "G:/eda/qdds/dds.fld" "" { Floorplan "G:/eda/qdds/dds.fld" "" "" { data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2] } "NODE_NAME" } }  } 0}  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[0] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[0\]" } } } } { "sld_dffex.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "G:/eda/qdds/dds.fld" "" { Floorplan "G:/eda/qdds/dds.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[0] } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\] " "Info: Node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\] uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\] " "Info: Port clear -- assigned as a global for destination node data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\] -- routed using non-global resources" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { data_v:u31|altsyncram:altsyncram_component|altsyncram_8it:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\]" } } } } { "sld_mod_ram_rom.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd" 160 -1 0 } } { "G:/eda/qdds/dds.fld" "" { Floorplan "G:/eda/qdds/dds.fld" "" "" { data_v:u31|altsyncram:altsyncram_component|altsyncram_8it:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[1\] " "Info: Port clear -- assigned as a global for destination node data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[1\] -- routed using non-global resources" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { data_v:u31|altsyncram:altsyncram_component|altsyncram_8it:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[1\]" } } } } { "sld_mod_ram_rom.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd" 160 -1 0 } } { "G:/eda/qdds/dds.fld" "" { Floorplan "G:/eda/qdds/dds.fld" "" "" { data_v:u31|altsyncram:altsyncram_component|altsyncram_8it:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[2\] " "Info: Port clear -- assigned as a global for destination node data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[2\] -- routed using non-global resources" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { data_v:u31|altsyncram:altsyncram_component|altsyncram_8it:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[2\]" } } } } { "sld_mod_ram_rom.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd" 160 -1 0 } } { "G:/eda/qdds/dds.fld" "" { Floorplan "G:/eda/qdds/dds.fld" "" "" { data_v:u31|altsyncram:altsyncram_component|altsyncram_8it:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[3\] " "Info: Port clear -- assigned as a global for destination node data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[3\] -- routed using non-global resources" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { data_v:u31|altsyncram:altsyncram_component|altsyncram_8it:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[3\]" } } } } { "sld_mod_ram_rom.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd" 160 -1 0 } } { "G:/eda/qdds/dds.fld" "" { Floorplan "G:/eda/qdds/dds.fld" "" "" { data_v:u31|altsyncram:altsyncram_component|altsyncram_8it:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[4\] " "Info: Port clear -- assigned as a global for destination node data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[4\] -- routed using non-global resources" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { data_v:u31|altsyncram:altsyncram_component|altsyncram_8it:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[4\]" } } } } { "sld_mod_ram_rom.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd" 160 -1 0 } } { "G:/eda/qdds/dds.fld" "" { Floorplan "G:/eda/qdds/dds.fld" "" "" { data_v:u31|altsyncram:altsyncram_component|altsyncram_8it:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[5\] " "Info: Port clear -- assigned as a global for destination node data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[5\] -- routed using non-global resources" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { data_v:u31|altsyncram:altsyncram_component|altsyncram_8it:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[5\]" } } } } { "sld_mod_ram_rom.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd" 160 -1 0 } } { "G:/eda/qdds/dds.fld" "" { Floorplan "G:/eda/qdds/dds.fld" "" "" { data_v:u31|altsyncram:altsyncram_component|altsyncram_8it:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[6\] " "Info: Port clear -- assigned as a global for destination node data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[6\] -- routed using non-global resources" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { data_v:u31|altsyncram:altsyncram_component|altsyncram_8it:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[6\]" } } } } { "sld_mod_ram_rom.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd" 160 -1 0 } } { "G:/eda/qdds/dds.fld" "" { Floorplan "G:/eda/qdds/dds.fld" "" "" { data_v:u31|altsyncram:altsyncram_component|altsyncram_8it:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[7\] " "Info: Port clear -- assigned as a global for destination node data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[7\] -- routed using non-global resources" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { data_v:u31|altsyncram:altsyncram_component|altsyncram_8it:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[7\]" } } } } { "sld_mod_ram_rom.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd" 160 -1 0 } } { "G:/eda/qdds/dds.fld" "" { Floorplan "G:/eda/qdds/dds.fld" "" "" { data_v:u31|altsyncram:altsyncram_component|altsyncram_8it:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7] } "NODE_NAME" } }  } 0}  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\]" } } } } { "sld_dffex.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "G:/eda/qdds/dds.fld" "" { Floorplan "G:/eda/qdds/dds.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0] } "NODE_NAME" } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jul 19 17:20:00 2008 " "Info: Processing ended: Sat Jul 19 17:20:00 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0}  } {  } 0}