dds.fit.qmsg

多功能函数发生器

{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\] Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|hub_tdo~1064 " "Info: Destination \"sld_hub:sld_hub_inst\|hub_tdo~1064\" may be non-global or may not use global clock" {  } { { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|hub_tdo~1065 " "Info: Destination \"sld_hub:sld_hub_inst\|hub_tdo~1065\" may be non-global or may not use global clock" {  } { { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg " "Info: Destination \"data_v:u31\|altsyncram:altsyncram_component\|altsyncram_8it:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg\" may be non-global or may not use global clock" {  } {  } 0}  } { { "sld_dffex.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[0\] Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[0\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|hub_tdo~1061 " "Info: Destination \"sld_hub:sld_hub_inst\|hub_tdo~1061\" may be non-global or may not use global clock" {  } { { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|hub_tdo~1062 " "Info: Destination \"sld_hub:sld_hub_inst\|hub_tdo~1062\" may be non-global or may not use global clock" {  } { { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg " "Info: Destination \"data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg\" may be non-global or may not use global clock" {  } {  } 0}  } { { "sld_dffex.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:3:IRF\|Q\[0\] Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:3:IRF\|Q\[0\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|hub_tdo~1071 " "Info: Destination \"sld_hub:sld_hub_inst\|hub_tdo~1071\" may be non-global or may not use global clock" {  } { { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|hub_tdo~1074 " "Info: Destination \"sld_hub:sld_hub_inst\|hub_tdo~1074\" may be non-global or may not use global clock" {  } { { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "data_juchi:u33\|altsyncram:altsyncram_component\|altsyncram_7vt:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg " "Info: Destination \"data_juchi:u33\|altsyncram:altsyncram_component\|altsyncram_7vt:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg\" may be non-global or may not use global clock" {  } {  } 0}  } { { "sld_dffex.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.795 ns register register " "Info: Estimated most critical path is register to register delay of 4.795 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr\|WORD_SR\[0\] 1 REG LAB_X22_Y5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X22_Y5; Fanout = 1; REG Node = 'data_f:u32\|altsyncram:altsyncram_component\|altsyncram_pht:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr\|WORD_SR\[0\]'" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "" { data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] } "NODE_NAME" } "" } } { "sld_rom_sr.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.639 ns) + CELL(0.590 ns) 2.229 ns sld_hub:sld_hub_inst\|hub_tdo~1062 2 COMB LAB_X16_Y9 1 " "Info: 2: + IC(1.639 ns) + CELL(0.590 ns) = 2.229 ns; Loc. = LAB_X16_Y9; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~1062'" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "2.229 ns" { data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~1062 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.461 ns) + CELL(0.292 ns) 3.982 ns sld_hub:sld_hub_inst\|hub_tdo~1063 3 COMB LAB_X20_Y6 1 " "Info: 3: + IC(1.461 ns) + CELL(0.292 ns) = 3.982 ns; Loc. = LAB_X20_Y6; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~1063'" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "1.753 ns" { sld_hub:sld_hub_inst|hub_tdo~1062 sld_hub:sld_hub_inst|hub_tdo~1063 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.075 ns) + CELL(0.738 ns) 4.795 ns sld_hub:sld_hub_inst\|hub_tdo 4 REG LAB_X20_Y6 0 " "Info: 4: + IC(0.075 ns) + CELL(0.738 ns) = 4.795 ns; Loc. = LAB_X20_Y6; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "0.813 ns" { sld_hub:sld_hub_inst|hub_tdo~1063 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.620 ns 33.79 % " "Info: Total cell delay = 1.620 ns ( 33.79 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.175 ns 66.21 % " "Info: Total interconnect delay = 3.175 ns ( 66.21 % )" {  } {  } 0}  } { { "G:/eda/qdds/db/dds_cmp.qrpt" "" { Report "G:/eda/qdds/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "G:/eda/qdds/db/dds.quartus_db" { Floorplan "G:/eda/qdds/" "" "4.795 ns" { data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~1062 sld_hub:sld_hub_inst|hub_tdo~1063 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } }  } 0}