dds.vhd

来自「多功能函数发生器」· VHDL 代码 · 共 69 行

library ieee;
use ieee.std_logic_1164.all;
entity dds is
port(clk: in std_logic;
    f_c:in std_logic_vector(5 downto 0);
     s_out: out std_logic_vector(7 downto 0);
     switch: in std_logic_vector(1 downto 0));
end dds;
 architecture behav of dds is
     component adder is
     port(load: in std_logic;
          a:in std_logic_vector(15 downto 0);
          b: in std_logic_vector(15 downto 0);
          s: out std_logic_vector(15 downto 0));
     end component;


 component d_switch is
     port(sw_out: out std_logic_vector(7 downto 0);
          sw_in0,sw_in1,sw_in2,sw_in3: in std_logic_vector(7 downto 0);
          c_switch:in std_logic_vector(1 downto 0));
 end component;


    
   component data_v is
     PORT(
		address		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		inclock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
   end component;
component data_f is
PORT
	(
		address		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		inclock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
	end component;
component data_juchi is
PORT
	(
		address		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		inclock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
	end component;
component data_sin is
PORT
	(
		address		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		inclock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
	end component;
	
 signal q1,fsw : std_logic_vector(15 downto 0);
 signal q2,q3,q4,q5:std_logic_vector(7 downto 0);
 begin
 fsw(15 downto 8)<="00000000";fsw(7 downto 2)<=f_c;fsw(1 downto 0)<="00";
  u1: adder port map(load=>clk,a=>fsw,b=>q1,s=>q1);
  u2: d_switch port map(sw_out=>s_out,c_switch=>switch,
                              sw_in0=>q2,sw_in1=>q3,sw_in2=>q4,sw_in3=>q5);
  u31: data_v port map(address=>q1(15 downto 8),inclock=>clk,q=>q2);
  u32: data_f port map(address=>q1(15 downto 8),inclock=>clk,q=>q3);
  u33: data_juchi port map (address=>q1(15 downto 8),inclock=>clk,q=>q4);
  u34: data_sin port map( address=>q1(15 downto 8),inclock=>clk, q=>q5);
 end architecture behav;