📄 dds.srr
字号:
u1.s_1.ADD_16x16_fast_I55_Y AO21 B In - 6.132 -
u1.s_1.ADD_16x16_fast_I55_Y AO21 Y Out 0.148 6.280 -
N368 Net - - 1.060 - 2
u1.s_1.ADD_16x16_fast_I60_un1_Y NAND3 A In - 7.340 -
u1.s_1.ADD_16x16_fast_I60_un1_Y NAND3 Y Out 0.056 7.396 -
I60_un1_Y Net - - 0.630 - 1
u1.s_1.ADD_16x16_fast_I60_Y AO21TTF C In - 8.026 -
u1.s_1.ADD_16x16_fast_I60_Y AO21TTF Y Out 0.068 8.094 -
N349 Net - - 0.630 - 1
u1.s_1.ADD_16x16_fast_I85_Y XOR2 B In - 8.724 -
u1.s_1.ADD_16x16_fast_I85_Y XOR2 Y Out 0.152 8.876 -
s_1[15] Net - - 0.630 - 1
u1.s[15] DFF D In - 9.506 -
=================================================================================================
Total path delay (propagation time + setup) of 9.754 is 1.304(13.4%) logic and 8.450(86.6%) route.
Path information for path number 4:
Requested Period: 8.384
- Setup time: 0.248
= Required time: 8.136
- Propagation time: 9.498
= Slack (non-critical) : -1.361
Number of logic level(s): 7
Starting point: u1.s[5] / Q
Ending point: u1.s[15] / D
The start point is clocked by dds|clk [rising] on pin CLK
The end point is clocked by dds|clk [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------------------
u1.s[5] DFF Q Out 0.200 0.200 -
q1[5] Net - - 1.480 - 3
u1.s_1.ADD_16x16_fast_I3_P0N OR2 B In - 1.680 -
u1.s_1.ADD_16x16_fast_I3_P0N OR2 Y Out 0.120 1.800 -
N186 Net - - 1.480 - 3
u1.s_1.ADD_16x16_fast_I17_Y NAND2 A In - 3.280 -
u1.s_1.ADD_16x16_fast_I17_Y NAND2 Y Out 0.152 3.432 -
N275 Net - - 1.480 - 3
u1.s_1.ADD_16x16_fast_I36_Y OAI21FTF B In - 4.912 -
u1.s_1.ADD_16x16_fast_I36_Y OAI21FTF Y Out 0.184 5.096 -
N303 Net - - 1.060 - 2
u1.s_1.ADD_16x16_fast_I55_Y AO21 C In - 6.156 -
u1.s_1.ADD_16x16_fast_I55_Y AO21 Y Out 0.104 6.260 -
N368 Net - - 1.060 - 2
u1.s_1.ADD_16x16_fast_I60_un1_Y NAND3 A In - 7.320 -
u1.s_1.ADD_16x16_fast_I60_un1_Y NAND3 Y Out 0.068 7.388 -
I60_un1_Y Net - - 0.630 - 1
u1.s_1.ADD_16x16_fast_I60_Y AO21TTF C In - 8.018 -
u1.s_1.ADD_16x16_fast_I60_Y AO21TTF Y Out 0.068 8.086 -
N349 Net - - 0.630 - 1
u1.s_1.ADD_16x16_fast_I85_Y XOR2 B In - 8.716 -
u1.s_1.ADD_16x16_fast_I85_Y XOR2 Y Out 0.152 8.868 -
s_1[15] Net - - 0.630 - 1
u1.s[15] DFF D In - 9.498 -
==================================================================================================
Total path delay (propagation time + setup) of 9.746 is 1.296(13.3%) logic and 8.450(86.7%) route.
Path information for path number 5:
Requested Period: 8.384
- Setup time: 0.248
= Required time: 8.136
- Propagation time: 9.474
= Slack (non-critical) : -1.338
Number of logic level(s): 7
Starting point: u1.s[5] / Q
Ending point: u1.s[15] / D
The start point is clocked by dds|clk [rising] on pin CLK
The end point is clocked by dds|clk [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------------
u1.s[5] DFF Q Out 0.200 0.200 -
q1[5] Net - - 1.480 - 3
u1.s_1.ADD_16x16_fast_I3_P0N OR2 B In - 1.680 -
u1.s_1.ADD_16x16_fast_I3_P0N OR2 Y Out 0.120 1.800 -
N186 Net - - 1.480 - 3
u1.s_1.ADD_16x16_fast_I17_Y NAND2 A In - 3.280 -
u1.s_1.ADD_16x16_fast_I17_Y NAND2 Y Out 0.152 3.432 -
N275 Net - - 1.480 - 3
u1.s_1.ADD_16x16_fast_I37_Y NOR2FT B In - 4.912 -
u1.s_1.ADD_16x16_fast_I37_Y NOR2FT Y Out 0.128 5.040 -
N304 Net - - 1.060 - 2
u1.s_1.ADD_16x16_fast_I55_Y AO21 B In - 6.100 -
u1.s_1.ADD_16x16_fast_I55_Y AO21 Y Out 0.148 6.248 -
N368 Net - - 1.060 - 2
u1.s_1.ADD_16x16_fast_I60_un1_Y NAND3 A In - 7.308 -
u1.s_1.ADD_16x16_fast_I60_un1_Y NAND3 Y Out 0.056 7.364 -
I60_un1_Y Net - - 0.630 - 1
u1.s_1.ADD_16x16_fast_I60_Y AO21TTF C In - 7.994 -
u1.s_1.ADD_16x16_fast_I60_Y AO21TTF Y Out 0.068 8.062 -
N349 Net - - 0.630 - 1
u1.s_1.ADD_16x16_fast_I85_Y XOR2 B In - 8.692 -
u1.s_1.ADD_16x16_fast_I85_Y XOR2 Y Out 0.152 8.844 -
s_1[15] Net - - 0.630 - 1
u1.s[15] DFF D In - 9.474 -
=================================================================================================
Total path delay (propagation time + setup) of 9.722 is 1.272(13.1%) logic and 8.450(86.9%) route.
##### END OF TIMING REPORT #####]
--------------------------------------------------------------------------------
Report for cell dds.behav
Core Cell usage:
cell count area count*area
AND2 12 1.0 12.0
AND3 1 1.0 1.0
AND3FTT 2 1.0 2.0
AO21 9 1.0 9.0
AO21TTF 4 1.0 4.0
AOI21 3 1.0 3.0
BFR 1 1.0 1.0
GND 7 0.0 0.0
MUX2H 24 1.0 24.0
NAND2 6 1.0 6.0
NAND3 4 1.0 4.0
NOR2 4 1.0 4.0
NOR2FT 4 1.0 4.0
NOR3 1 1.0 1.0
OAI21FTF 2 1.0 2.0
OR2 5 1.0 5.0
PWR 7 0.0 0.0
XOR2 15 1.0 15.0
XOR2FT 4 1.0 4.0
altsyncram_work_dds_behav_1 1 0.0 0.0
altsyncram_work_dds_behav_3 1 0.0 0.0
altsyncram_work_dds_behav_5 1 0.0 0.0
altsyncram_work_dds_behav_7 1 0.0 0.0
DFF 14 1.0 14.0
----- ----------
TOTAL 133 115.0
IO Cell usage:
cell count
GL33 1
IB33 8
OB33PH 8
-----
TOTAL 17
Core Cells : 115 of 105376 (0%)
IO Cells : 17 of 204 (8%)
RAM/ROM Usage Summary
Block Rams : 0 of 6 (0%)
Mapper successful!
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Jul 19 16:07:10 2008
###########################################################]
Total runtime: 00h:00m:05s realtime
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