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📄 dds.srr

📁 多功能函数发生器
💻 SRR
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====================================
Detailed Report for Clock: dds|clk
====================================



Starting Points with Worst Slack
********************************

             Starting                                  Arrival           
Instance     Reference     Type     Pin     Net        Time        Slack 
             Clock                                                       
-------------------------------------------------------------------------
u1.s[2]      dds|clk       DFF      Q       q1[2]      0.200       -1.480
u1.s[6]      dds|clk       DFF      Q       q1[6]      0.200       -1.394
u1.s[5]      dds|clk       DFF      Q       q1[5]      0.200       -1.361
u1.s[4]      dds|clk       DFF      Q       q1[4]      0.200       -0.921
u1.s[8]      dds|clk       DFF      Q       q1[8]      0.200       -0.893
u1.s[7]      dds|clk       DFF      Q       q1[7]      0.200       -0.686
u1.s[10]     dds|clk       DFF      Q       q1[10]     0.200       -0.620
u1.s[9]      dds|clk       DFF      Q       q1[9]      0.200       -0.588
u1.s[3]      dds|clk       DFF      Q       q1[3]      0.200       -0.566
u1.s[11]     dds|clk       DFF      Q       q1[11]     0.200       0.276 
=========================================================================


Ending Points with Worst Slack
******************************

             Starting                                   Required           
Instance     Reference     Type     Pin     Net         Time         Slack 
             Clock                                                         
---------------------------------------------------------------------------
u1.s[14]     dds|clk       DFF      D       s_1[14]     8.136        -1.480
u1.s[15]     dds|clk       DFF      D       s_1[15]     8.136        -1.394
u1.s[11]     dds|clk       DFF      D       s_1[11]     8.136        -0.893
u1.s[10]     dds|clk       DFF      D       s_1[10]     8.136        -0.874
u1.s[13]     dds|clk       DFF      D       s_1[13]     8.136        -0.474
u1.s[12]     dds|clk       DFF      D       s_1[12]     8.136        -0.417
u1.s[6]      dds|clk       DFF      D       s_1[6]      8.136        -0.092
u1.s[7]      dds|clk       DFF      D       s_1[7]      8.136        0.006 
u1.s[9]      dds|clk       DFF      D       s_1[9]      8.136        0.204 
u1.s[8]      dds|clk       DFF      D       s_1[8]      8.136        0.465 
===========================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Requested Period:                        8.384
    - Setup time:                            0.248
    = Required time:                         8.136

    - Propagation time:                      9.616
    = Slack (critical) :                     -1.480

    Number of logic level(s):                6
    Starting point:                          u1.s[2] / Q
    Ending point:                            u1.s[14] / D
    The start point is clocked by            dds|clk [rising] on pin CLK
    The end   point is clocked by            dds|clk [rising] on pin CLK

Instance / Net                                                 Pin      Pin               Arrival     No. of    
Name                                               Type        Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------
u1.s[2]                                            DFF         Q        Out     0.200     0.200       -         
q1[2]                                              Net         -        -       1.060     -           2         
u1.s_1.resyn_0.u1.s_1.ADD_16x16_fast_I0_CO1        AND2        B        In      -         1.260       -         
u1.s_1.resyn_0.u1.s_1.ADD_16x16_fast_I0_CO1        AND2        Y        Out     0.164     1.424       -         
N176                                               Net         -        -       2.330     -           5         
u1.s_1.resyn_0.u1.s_1.ADD_16x16_fast_I22_Y         AO21        A        In      -         3.754       -         
u1.s_1.resyn_0.u1.s_1.ADD_16x16_fast_I22_Y         AO21        Y        Out     0.168     3.922       -         
N280                                               Net         -        -       1.900     -           4         
u1.s_1.resyn_0.u1.s_1.ADD_16x16_fast_I38_Y         AO21        B        In      -         5.822       -         
u1.s_1.resyn_0.u1.s_1.ADD_16x16_fast_I38_Y         AO21        Y        Out     0.148     5.970       -         
N305                                               Net         -        -       1.480     -           3         
u1.s_1.resyn_0.u1.s_1.ADD_16x16_fast_I61_un1_Y     NAND3       A        In      -         7.450       -         
u1.s_1.resyn_0.u1.s_1.ADD_16x16_fast_I61_un1_Y     NAND3       Y        Out     0.056     7.506       -         
I61_un1_Y                                          Net         -        -       0.630     -           1         
u1.s_1.resyn_0.u1.s_1.ADD_16x16_fast_I61_Y         AO21TTF     C        In      -         8.136       -         
u1.s_1.resyn_0.u1.s_1.ADD_16x16_fast_I61_Y         AO21TTF     Y        Out     0.068     8.204       -         
N351                                               Net         -        -       0.630     -           1         
u1.s_1.resyn_0.u1.s_1.ADD_16x16_fast_I84_Y         XOR2        B        In      -         8.834       -         
u1.s_1.resyn_0.u1.s_1.ADD_16x16_fast_I84_Y         XOR2        Y        Out     0.152     8.986       -         
s_1[14]                                            Net         -        -       0.630     -           1         
u1.s[14]                                           DFF         D        In      -         9.616       -         
================================================================================================================
Total path delay (propagation time + setup) of 9.864 is 1.204(12.2%) logic and 8.660(87.8%) route.


Path information for path number 2: 
    Requested Period:                        8.384
    - Setup time:                            0.248
    = Required time:                         8.136

    - Propagation time:                      9.530
    = Slack (non-critical) :                 -1.394

    Number of logic level(s):                7
    Starting point:                          u1.s[6] / Q
    Ending point:                            u1.s[15] / D
    The start point is clocked by            dds|clk [rising] on pin CLK
    The end   point is clocked by            dds|clk [rising] on pin CLK

Instance / Net                                   Pin      Pin               Arrival     No. of    
Name                                Type         Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------
u1.s[6]                             DFF          Q        Out     0.200     0.200       -         
q1[6]                               Net          -        -       1.480     -           3         
u1.s_1.ADD_16x16_fast_I4_P0N        OR2          B        In      -         1.680       -         
u1.s_1.ADD_16x16_fast_I4_P0N        OR2          Y        Out     0.120     1.800       -         
N189                                Net          -        -       1.480     -           3         
u1.s_1.ADD_16x16_fast_I17_Y         NAND2        B        In      -         3.280       -         
u1.s_1.ADD_16x16_fast_I17_Y         NAND2        Y        Out     0.184     3.464       -         
N275                                Net          -        -       1.480     -           3         
u1.s_1.ADD_16x16_fast_I36_Y         OAI21FTF     B        In      -         4.944       -         
u1.s_1.ADD_16x16_fast_I36_Y         OAI21FTF     Y        Out     0.184     5.128       -         
N303                                Net          -        -       1.060     -           2         
u1.s_1.ADD_16x16_fast_I55_Y         AO21         C        In      -         6.188       -         
u1.s_1.ADD_16x16_fast_I55_Y         AO21         Y        Out     0.104     6.292       -         
N368                                Net          -        -       1.060     -           2         
u1.s_1.ADD_16x16_fast_I60_un1_Y     NAND3        A        In      -         7.352       -         
u1.s_1.ADD_16x16_fast_I60_un1_Y     NAND3        Y        Out     0.068     7.420       -         
I60_un1_Y                           Net          -        -       0.630     -           1         
u1.s_1.ADD_16x16_fast_I60_Y         AO21TTF      C        In      -         8.050       -         
u1.s_1.ADD_16x16_fast_I60_Y         AO21TTF      Y        Out     0.068     8.118       -         
N349                                Net          -        -       0.630     -           1         
u1.s_1.ADD_16x16_fast_I85_Y         XOR2         B        In      -         8.748       -         
u1.s_1.ADD_16x16_fast_I85_Y         XOR2         Y        Out     0.152     8.900       -         
s_1[15]                             Net          -        -       0.630     -           1         
u1.s[15]                            DFF          D        In      -         9.530       -         
==================================================================================================
Total path delay (propagation time + setup) of 9.778 is 1.328(13.6%) logic and 8.450(86.4%) route.


Path information for path number 3: 
    Requested Period:                        8.384
    - Setup time:                            0.248
    = Required time:                         8.136

    - Propagation time:                      9.506
    = Slack (non-critical) :                 -1.370

    Number of logic level(s):                7
    Starting point:                          u1.s[6] / Q
    Ending point:                            u1.s[15] / D
    The start point is clocked by            dds|clk [rising] on pin CLK
    The end   point is clocked by            dds|clk [rising] on pin CLK

Instance / Net                                  Pin      Pin               Arrival     No. of    
Name                                Type        Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------
u1.s[6]                             DFF         Q        Out     0.200     0.200       -         
q1[6]                               Net         -        -       1.480     -           3         
u1.s_1.ADD_16x16_fast_I4_P0N        OR2         B        In      -         1.680       -         
u1.s_1.ADD_16x16_fast_I4_P0N        OR2         Y        Out     0.120     1.800       -         
N189                                Net         -        -       1.480     -           3         
u1.s_1.ADD_16x16_fast_I17_Y         NAND2       B        In      -         3.280       -         
u1.s_1.ADD_16x16_fast_I17_Y         NAND2       Y        Out     0.184     3.464       -         
N275                                Net         -        -       1.480     -           3         
u1.s_1.ADD_16x16_fast_I37_Y         NOR2FT      B        In      -         4.944       -         
u1.s_1.ADD_16x16_fast_I37_Y         NOR2FT      Y        Out     0.128     5.072       -         
N304                                Net         -        -       1.060     -           2         

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