dds.srr

多功能函数发生器

#Build: Synplify Pro 9.0.1, Build 024R, Nov 13 2007
#install: C:\Program Files\Synplicity\fpga_901
#OS: Windows XP 5.1
#Hostname: QIN

#Implementation: rev_1

#Sat Jul 19 16:07:05 2008

$ Start of Compile
#Sat Jul 19 16:07:05 2008

Synplicity VHDL Compiler, version 1.0, Build 158R, built Nov 14 2007
Copyright (C) 1994-2007, Synplicity Inc.  All Rights Reserved

@N: CD720 :"C:\Program Files\Synplicity\fpga_901\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"G:\eda\qdds\dds.vhd":3:7:3:9|Top entity is set to dds.
VHDL syntax check successful!
@N: CD630 :"G:\eda\qdds\dds.vhd":3:7:3:9|Synthesizing work.dds.behav 
@N: CD630 :"G:\eda\qdds\data_sin.vhd":39:7:39:14|Synthesizing work.data_sin.syn 
@N: CD630 :"G:\eda\qdds\data_sin.vhd":55:11:55:20|Synthesizing altera_mf.altsyncram_work_dds_behav_1.syn_black_box 
Post processing for altera_mf.altsyncram_work_dds_behav_1.syn_black_box
Post processing for work.data_sin.syn
@N: CD630 :"G:\eda\qdds\data_juchi.vhd":39:7:39:16|Synthesizing work.data_juchi.syn 
@N: CD630 :"G:\eda\qdds\data_juchi.vhd":55:11:55:20|Synthesizing altera_mf.altsyncram_work_dds_behav_3.syn_black_box 
Post processing for altera_mf.altsyncram_work_dds_behav_3.syn_black_box
Post processing for work.data_juchi.syn
@N: CD630 :"G:\eda\qdds\data_f.vhd":39:7:39:12|Synthesizing work.data_f.syn 
@N: CD630 :"G:\eda\qdds\data_f.vhd":55:11:55:20|Synthesizing altera_mf.altsyncram_work_dds_behav_5.syn_black_box 
Post processing for altera_mf.altsyncram_work_dds_behav_5.syn_black_box
Post processing for work.data_f.syn
@N: CD630 :"G:\eda\qdds\data_v.vhd":39:7:39:12|Synthesizing work.data_v.syn 
@N: CD630 :"G:\eda\qdds\data_v.vhd":55:11:55:20|Synthesizing altera_mf.altsyncram_work_dds_behav_7.syn_black_box 
Post processing for altera_mf.altsyncram_work_dds_behav_7.syn_black_box
Post processing for work.data_v.syn
@N: CD630 :"G:\eda\qdds\d_switch.vhd":3:7:3:14|Synthesizing work.d_switch.behav 
@W: CG296 :"G:\eda\qdds\d_switch.vhd":10:0:10:6|Incomplete sensitivity list - assuming completeness
@W: CG290 :"G:\eda\qdds\d_switch.vhd":15:21:15:26|Referenced variable sw_in2 is not in sensitivity list
@W: CG290 :"G:\eda\qdds\d_switch.vhd":14:21:14:26|Referenced variable sw_in1 is not in sensitivity list
@W: CG290 :"G:\eda\qdds\d_switch.vhd":13:21:13:26|Referenced variable sw_in0 is not in sensitivity list
@W: CG290 :"G:\eda\qdds\d_switch.vhd":16:21:16:26|Referenced variable sw_in3 is not in sensitivity list
Post processing for work.d_switch.behav
@N: CD630 :"G:\eda\qdds\adder.vhd":4:7:4:11|Synthesizing work.adder.behav 
Post processing for work.adder.behav
Post processing for work.dds.behav
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Jul 19 16:07:06 2008

###########################################################]
Synplicity Proasic Technology Mapper, Version 9.0.0, Build 145R, Built Nov 19 2007 20:46:13
Copyright (C) 1994-2007, Synplicity Inc.  All Rights Reserved
Product Version Version 9.0.1
@N: MF249 |Running in 32-bit mode.
@N: MF258 |Gated clock conversion disabled 


Automatic dissolve during optimization of view:work.dds(behav) of u34(data_sin)
Automatic dissolve during optimization of view:work.dds(behav) of u33(data_juchi)
Automatic dissolve during optimization of view:work.dds(behav) of u32(data_f)
Automatic dissolve during optimization of view:work.dds(behav) of u31(data_v)
@N: MT206 |Autoconstrain Mode is ON
RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 36MB peak: 37MB)
@N: MF176 |Default generator successful 

Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 37MB peak: 38MB)
@W: BN116 :"g:\eda\qdds\adder.vhd":14:0:14:1|Removing sequential instance u1.s[1] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"g:\eda\qdds\adder.vhd":14:0:14:1|Removing sequential instance u1.s[0] of view:PrimLib.dff(prim) because there are no references to its outputs 

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 37MB peak: 38MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 37MB peak: 38MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 37MB peak: 38MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 37MB peak: 38MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 37MB peak: 38MB)

Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 38MB peak: 38MB)

High Fanout Net Report
**********************

Driver Instance / Pin Name     Fanout, notes
--------------------------------------------
switch_pad[1] / Y              16           
============================================

Promoting Net clk_c on GL33  clk_pad
Buffering switch_c[1], fanout 16 segments 2

Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 37MB peak: 38MB)

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 37MB peak: 39MB)

Added 1 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 37MB peak: 39MB)
Writing Analyst data base G:\eda\qdds\rev_1\dds.srm
@N: BN225 |Writing default property annotation file G:\eda\qdds\rev_1\dds.map.
Writing EDIF Netlist and constraint files
Version 9.0.1
Found clock dds|clk with period 8.38ns 
@W: MT246 |Blackbox altsyncram_work_dds_behav_7 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 |Blackbox altsyncram_work_dds_behav_5 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 |Blackbox altsyncram_work_dds_behav_3 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 |Blackbox altsyncram_work_dds_behav_1 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 


##### START OF TIMING REPORT #####[
# Timing Report written on Sat Jul 19 16:07:10 2008
#


Top view:               dds
Requested Frequency:    119.3 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: -1.480

                   Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group                
------------------------------------------------------------------------------------------------------------------------
dds|clk            119.3 MHz     101.4 MHz     8.384         9.864         -1.480     inferred     Autoconstr_clkgroup_0
========================================================================================================================





Clock Relationships
*******************

Clocks             |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
----------------------------------------------------------------------------------------------------------
Starting  Ending   |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
----------------------------------------------------------------------------------------------------------
dds|clk   dds|clk  |  8.384       -1.480  |  No paths    -      |  No paths    -      |  No paths    -    
==========================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found