dds.map.eqn

多功能函数发生器

--Z1_q_a[2] is data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|altsyncram_6hb2:altsyncram1|q_a[2]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8, Port B Logical Depth: 256, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
Z1_q_a[2]_PORT_A_data_in = VCC;
Z1_q_a[2]_PORT_A_data_in_reg = DFFE(Z1_q_a[2]_PORT_A_data_in, Z1_q_a[2]_clock_0, , , );
Z1_q_a[2]_PORT_B_data_in = T4_ram_rom_data_reg[2];
Z1_q_a[2]_PORT_B_data_in_reg = DFFE(Z1_q_a[2]_PORT_B_data_in, Z1_q_a[2]_clock_1, , , );
Z1_q_a[2]_PORT_A_address = BUS(C1_s[8], C1_s[9], C1_s[10], C1_s[11], C1_s[12], C1_s[13], C1_s[14], C1_s[15]);
Z1_q_a[2]_PORT_A_address_reg = DFFE(Z1_q_a[2]_PORT_A_address, Z1_q_a[2]_clock_0, , , );
Z1_q_a[2]_PORT_B_address = BUS(T4_ram_rom_addr_reg[0], T4_ram_rom_addr_reg[1], T4_ram_rom_addr_reg[2], T4_ram_rom_addr_reg[3], T4_ram_rom_addr_reg[4], T4_ram_rom_addr_reg[5], T4_ram_rom_addr_reg[6], T4_ram_rom_addr_reg[7]);
Z1_q_a[2]_PORT_B_address_reg = DFFE(Z1_q_a[2]_PORT_B_address, Z1_q_a[2]_clock_1, , , );
Z1_q_a[2]_PORT_A_write_enable = GND;
Z1_q_a[2]_PORT_A_write_enable_reg = DFFE(Z1_q_a[2]_PORT_A_write_enable, Z1_q_a[2]_clock_0, , , );
Z1_q_a[2]_PORT_B_write_enable = T4L2;
Z1_q_a[2]_PORT_B_write_enable_reg = DFFE(Z1_q_a[2]_PORT_B_write_enable, Z1_q_a[2]_clock_1, , , );
Z1_q_a[2]_clock_0 = clk;
Z1_q_a[2]_clock_1 = A1L5;
Z1_q_a[2]_PORT_A_data_out = MEMORY(Z1_q_a[2]_PORT_A_data_in_reg, Z1_q_a[2]_PORT_B_data_in_reg, Z1_q_a[2]_PORT_A_address_reg, Z1_q_a[2]_PORT_B_address_reg, Z1_q_a[2]_PORT_A_write_enable_reg, Z1_q_a[2]_PORT_B_write_enable_reg, , , Z1_q_a[2]_clock_0, Z1_q_a[2]_clock_1, , , , );
Z1_q_a[2] = Z1_q_a[2]_PORT_A_data_out[0];

--Z1_q_b[2] is data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|altsyncram_6hb2:altsyncram1|q_b[2]
Z1_q_b[2]_PORT_A_data_in = VCC;
Z1_q_b[2]_PORT_A_data_in_reg = DFFE(Z1_q_b[2]_PORT_A_data_in, Z1_q_b[2]_clock_0, , , );
Z1_q_b[2]_PORT_B_data_in = T4_ram_rom_data_reg[2];
Z1_q_b[2]_PORT_B_data_in_reg = DFFE(Z1_q_b[2]_PORT_B_data_in, Z1_q_b[2]_clock_1, , , );
Z1_q_b[2]_PORT_A_address = BUS(C1_s[8], C1_s[9], C1_s[10], C1_s[11], C1_s[12], C1_s[13], C1_s[14], C1_s[15]);
Z1_q_b[2]_PORT_A_address_reg = DFFE(Z1_q_b[2]_PORT_A_address, Z1_q_b[2]_clock_0, , , );
Z1_q_b[2]_PORT_B_address = BUS(T4_ram_rom_addr_reg[0], T4_ram_rom_addr_reg[1], T4_ram_rom_addr_reg[2], T4_ram_rom_addr_reg[3], T4_ram_rom_addr_reg[4], T4_ram_rom_addr_reg[5], T4_ram_rom_addr_reg[6], T4_ram_rom_addr_reg[7]);
Z1_q_b[2]_PORT_B_address_reg = DFFE(Z1_q_b[2]_PORT_B_address, Z1_q_b[2]_clock_1, , , );
Z1_q_b[2]_PORT_A_write_enable = GND;
Z1_q_b[2]_PORT_A_write_enable_reg = DFFE(Z1_q_b[2]_PORT_A_write_enable, Z1_q_b[2]_clock_0, , , );
Z1_q_b[2]_PORT_B_write_enable = T4L2;
Z1_q_b[2]_PORT_B_write_enable_reg = DFFE(Z1_q_b[2]_PORT_B_write_enable, Z1_q_b[2]_clock_1, , , );
Z1_q_b[2]_clock_0 = clk;
Z1_q_b[2]_clock_1 = A1L5;
Z1_q_b[2]_PORT_B_data_out = MEMORY(Z1_q_b[2]_PORT_A_data_in_reg, Z1_q_b[2]_PORT_B_data_in_reg, Z1_q_b[2]_PORT_A_address_reg, Z1_q_b[2]_PORT_B_address_reg, Z1_q_b[2]_PORT_A_write_enable_reg, Z1_q_b[2]_PORT_B_write_enable_reg, , , Z1_q_b[2]_clock_0, Z1_q_b[2]_clock_1, , , , );
Z1_q_b[2] = Z1_q_b[2]_PORT_B_data_out[0];


--D1L6 is d_switch:u2|sw_out[2]~113
--operation mode is normal

D1L6 = switch[0] & (D1L5 & (Z1_q_a[2]) # !D1L5 & V1_q_a[2]) # !switch[0] & (D1L5);


--X1_q_a[3] is data_juchi:u33|altsyncram:altsyncram_component|altsyncram_7vt:auto_generated|altsyncram_fnb2:altsyncram1|q_a[3]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8, Port B Logical Depth: 256, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
X1_q_a[3]_PORT_A_data_in = VCC;
X1_q_a[3]_PORT_A_data_in_reg = DFFE(X1_q_a[3]_PORT_A_data_in, X1_q_a[3]_clock_0, , , );
X1_q_a[3]_PORT_B_data_in = T3_ram_rom_data_reg[3];
X1_q_a[3]_PORT_B_data_in_reg = DFFE(X1_q_a[3]_PORT_B_data_in, X1_q_a[3]_clock_1, , , );
X1_q_a[3]_PORT_A_address = BUS(C1_s[8], C1_s[9], C1_s[10], C1_s[11], C1_s[12], C1_s[13], C1_s[14], C1_s[15]);
X1_q_a[3]_PORT_A_address_reg = DFFE(X1_q_a[3]_PORT_A_address, X1_q_a[3]_clock_0, , , );
X1_q_a[3]_PORT_B_address = BUS(T3_ram_rom_addr_reg[0], T3_ram_rom_addr_reg[1], T3_ram_rom_addr_reg[2], T3_ram_rom_addr_reg[3], T3_ram_rom_addr_reg[4], T3_ram_rom_addr_reg[5], T3_ram_rom_addr_reg[6], T3_ram_rom_addr_reg[7]);
X1_q_a[3]_PORT_B_address_reg = DFFE(X1_q_a[3]_PORT_B_address, X1_q_a[3]_clock_1, , , );
X1_q_a[3]_PORT_A_write_enable = GND;
X1_q_a[3]_PORT_A_write_enable_reg = DFFE(X1_q_a[3]_PORT_A_write_enable, X1_q_a[3]_clock_0, , , );
X1_q_a[3]_PORT_B_write_enable = T3L2;
X1_q_a[3]_PORT_B_write_enable_reg = DFFE(X1_q_a[3]_PORT_B_write_enable, X1_q_a[3]_clock_1, , , );
X1_q_a[3]_clock_0 = clk;
X1_q_a[3]_clock_1 = A1L5;
X1_q_a[3]_PORT_A_data_out = MEMORY(X1_q_a[3]_PORT_A_data_in_reg, X1_q_a[3]_PORT_B_data_in_reg, X1_q_a[3]_PORT_A_address_reg, X1_q_a[3]_PORT_B_address_reg, X1_q_a[3]_PORT_A_write_enable_reg, X1_q_a[3]_PORT_B_write_enable_reg, , , X1_q_a[3]_clock_0, X1_q_a[3]_clock_1, , , , );
X1_q_a[3] = X1_q_a[3]_PORT_A_data_out[0];

--X1_q_b[3] is data_juchi:u33|altsyncram:altsyncram_component|altsyncram_7vt:auto_generated|altsyncram_fnb2:altsyncram1|q_b[3]
X1_q_b[3]_PORT_A_data_in = VCC;
X1_q_b[3]_PORT_A_data_in_reg = DFFE(X1_q_b[3]_PORT_A_data_in, X1_q_b[3]_clock_0, , , );
X1_q_b[3]_PORT_B_data_in = T3_ram_rom_data_reg[3];
X1_q_b[3]_PORT_B_data_in_reg = DFFE(X1_q_b[3]_PORT_B_data_in, X1_q_b[3]_clock_1, , , );
X1_q_b[3]_PORT_A_address = BUS(C1_s[8], C1_s[9], C1_s[10], C1_s[11], C1_s[12], C1_s[13], C1_s[14], C1_s[15]);
X1_q_b[3]_PORT_A_address_reg = DFFE(X1_q_b[3]_PORT_A_address, X1_q_b[3]_clock_0, , , );
X1_q_b[3]_PORT_B_address = BUS(T3_ram_rom_addr_reg[0], T3_ram_rom_addr_reg[1], T3_ram_rom_addr_reg[2], T3_ram_rom_addr_reg[3], T3_ram_rom_addr_reg[4], T3_ram_rom_addr_reg[5], T3_ram_rom_addr_reg[6], T3_ram_rom_addr_reg[7]);
X1_q_b[3]_PORT_B_address_reg = DFFE(X1_q_b[3]_PORT_B_address, X1_q_b[3]_clock_1, , , );
X1_q_b[3]_PORT_A_write_enable = GND;
X1_q_b[3]_PORT_A_write_enable_reg = DFFE(X1_q_b[3]_PORT_A_write_enable, X1_q_b[3]_clock_0, , , );
X1_q_b[3]_PORT_B_write_enable = T3L2;
X1_q_b[3]_PORT_B_write_enable_reg = DFFE(X1_q_b[3]_PORT_B_write_enable, X1_q_b[3]_clock_1, , , );
X1_q_b[3]_clock_0 = clk;
X1_q_b[3]_clock_1 = A1L5;
X1_q_b[3]_PORT_B_data_out = MEMORY(X1_q_b[3]_PORT_A_data_in_reg, X1_q_b[3]_PORT_B_data_in_reg, X1_q_b[3]_PORT_A_address_reg, X1_q_b[3]_PORT_B_address_reg, X1_q_b[3]_PORT_A_write_enable_reg, X1_q_b[3]_PORT_B_write_enable_reg, , , X1_q_b[3]_clock_0, X1_q_b[3]_clock_1, , , , );
X1_q_b[3] = X1_q_b[3]_PORT_B_data_out[0];


--V1_q_a[3] is data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1|q_a[3]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8, Port B Logical Depth: 256, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
V1_q_a[3]_PORT_A_data_in = VCC;
V1_q_a[3]_PORT_A_data_in_reg = DFFE(V1_q_a[3]_PORT_A_data_in, V1_q_a[3]_clock_0, , , );
V1_q_a[3]_PORT_B_data_in = T2_ram_rom_data_reg[3];
V1_q_a[3]_PORT_B_data_in_reg = DFFE(V1_q_a[3]_PORT_B_data_in, V1_q_a[3]_clock_1, , , );
V1_q_a[3]_PORT_A_address = BUS(C1_s[8], C1_s[9], C1_s[10], C1_s[11], C1_s[12], C1_s[13], C1_s[14], C1_s[15]);
V1_q_a[3]_PORT_A_address_reg = DFFE(V1_q_a[3]_PORT_A_address, V1_q_a[3]_clock_0, , , );
V1_q_a[3]_PORT_B_address = BUS(T2_ram_rom_addr_reg[0], T2_ram_rom_addr_reg[1], T2_ram_rom_addr_reg[2], T2_ram_rom_addr_reg[3], T2_ram_rom_addr_reg[4], T2_ram_rom_addr_reg[5], T2_ram_rom_addr_reg[6], T2_ram_rom_addr_reg[7]);
V1_q_a[3]_PORT_B_address_reg = DFFE(V1_q_a[3]_PORT_B_address, V1_q_a[3]_clock_1, , , );
V1_q_a[3]_PORT_A_write_enable = GND;
V1_q_a[3]_PORT_A_write_enable_reg = DFFE(V1_q_a[3]_PORT_A_write_enable, V1_q_a[3]_clock_0, , , );
V1_q_a[3]_PORT_B_write_enable = T2L2;
V1_q_a[3]_PORT_B_write_enable_reg = DFFE(V1_q_a[3]_PORT_B_write_enable, V1_q_a[3]_clock_1, , , );
V1_q_a[3]_clock_0 = clk;
V1_q_a[3]_clock_1 = A1L5;
V1_q_a[3]_PORT_A_data_out = MEMORY(V1_q_a[3]_PORT_A_data_in_reg, V1_q_a[3]_PORT_B_data_in_reg, V1_q_a[3]_PORT_A_address_reg, V1_q_a[3]_PORT_B_address_reg, V1_q_a[3]_PORT_A_write_enable_reg, V1_q_a[3]_PORT_B_write_enable_reg, , , V1_q_a[3]_clock_0, V1_q_a[3]_clock_1, , , , );
V1_q_a[3] = V1_q_a[3]_PORT_A_data_out[0];

--V1_q_b[3] is data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1|q_b[3]
V1_q_b[3]_PORT_A_data_in = VCC;
V1_q_b[3]_PORT_A_data_in_reg = DFFE(V1_q_b[3]_PORT_A_data_in, V1_q_b[3]_clock_0, , , );
V1_q_b[3]_PORT_B_data_in = T2_ram_rom_data_reg[3];
V1_q_b[3]_PORT_B_data_in_reg = DFFE(V1_q_b[3]_PORT_B_data_in, V1_q_b[3]_clock_1, , , );
V1_q_b[3]_PORT_A_address = BUS(C1_s[8], C1_s[9], C1_s[10], C1_s[11], C1_s[12], C1_s[13], C1_s[14], C1_s[15]);
V1_q_b[3]_PORT_A_address_reg = DFFE(V1_q_b[3]_PORT_A_address, V1_q_b[3]_clock_0, , , );
V1_q_b[3]_PORT_B_address = BUS(T2_ram_rom_addr_reg[0], T2_ram_rom_addr_reg[1], T2_ram_rom_addr_reg[2], T2_ram_rom_addr_reg[3], T2_ram_rom_addr_reg[4], T2_ram_rom_addr_reg[5], T2_ram_rom_addr_reg[6], T2_ram_rom_addr_reg[7]);
V1_q_b[3]_PORT_B_address_reg = DFFE(V1_q_b[3]_PORT_B_address, V1_q_b[3]_clock_1, , , );
V1_q_b[3]_PORT_A_write_enable = GND;
V1_q_b[3]_PORT_A_write_enable_reg = DFFE(V1_q_b[3]_PORT_A_write_enable, V1_q_b[3]_clock_0, , , );
V1_q_b[3]_PORT_B_write_enable = T2L2;
V1_q_b[3]_PORT_B_write_enable_reg = DFFE(V1_q_b[3]_PORT_B_write_enable, V1_q_b[3]_clock_1, , , );
V1_q_b[3]_clock_0 = clk;
V1_q_b[3]_clock_1 = A1L5;
V1_q_b[3]_PORT_B_data_out = MEMORY(V1_q_b[3]_PORT_A_data_in_reg, V1_q_b[3]_PORT_B_data_in_reg, V1_q_b[3]_PORT_A_address_reg, V1_q_b[3]_PORT_B_address_reg, V1_q_b[3]_PORT_A_write_enable_reg, V1_q_b[3]_PORT_B_write_enable_reg, , , V1_q_b[3]_clock_0, V1_q_b[3]_clock_1, , , , );
V1_q_b[3] = V1_q_b[3]_PORT_B_data_out[0];


--S1_q_a[3] is data_v:u31|altsyncram:altsyncram_component|altsyncram_8it:auto_generated|altsyncram_iab2:altsyncram1|q_a[3]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8, Port B Logical Depth: 256, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
S1_q_a[3]_PORT_A_data_in = VCC;
S1_q_a[3]_PORT_A_data_in_reg = DFFE(S1_q_a[3]_PORT_A_data_in, S1_q_a[3]_clock_0, , , );
S1_q_a[3]_PORT_B_data_in = T1_ram_rom_data_reg[3];
S1_q_a[3]_PORT_B_data_in_reg = DFFE(S1_q_a[3]_PORT_B_data_in, S1_q_a[3]_clock_1, , , );
S1_q_a[3]_PORT_A_address = BUS(C1_s[8], C1_s[9], C1_s[10], C1_s[11], C1_s[12], C1_s[13], C1_s[14], C1_s[15]);
S1_q_a[3]_PORT_A_address_reg = DFFE(S1_q_a[3]_PORT_A_address, S1_q_a[3]_clock_0, , , );
S1_q_a[3]_PORT_B_address = BUS(T1_ram_rom_addr_reg[0], T1_ram_rom_addr_reg[1], T1_ram_rom_addr_reg[2], T1_ram_rom_addr_reg[3], T1_ram_rom_addr_reg[4], T1_ram_rom_addr_reg[5], T1_ram_rom_addr_reg[6], T1_ram_rom_addr_reg[7]);
S1_q_a[3]_PORT_B_address_reg = DFFE(S1_q_a[3]_PORT_B_address, S1_q_a[3]_clock_1, , , );
S1_q_a[3]_PORT_A_write_enable = GND;
S1_q_a[3]_PORT_A_write_enable_reg = DFFE(S1_q_a[3]_PORT_A_write_enable, S1_q_a[3]_clock_0, , , );
S1_q_a[3]_PORT_B_write_enable = T1L2;
S1_q_a[3]_PORT_B_write_enable_reg = DFFE(S1_q_a[3]_PORT_B_write_enable, S1_q_a[3]_clock_1, , , );
S1_q_a[3]_clock_0 = clk;
S1_q_a[3]_clock_1 = A1L5;
S1_q_a[3]_PORT_A_data_out = MEMORY(S1_q_a[3]_PORT_A_data_in_reg, S1_q_a[3]_PORT_B_data_in_reg, S1_q_a[3]_PORT_A_address_reg, S1_q_a[3]_PORT_B_address_reg, S1_q_a[3]_PORT_A_write_enable_reg, S1_q_a[3]_PORT_B_write_enable_reg, , , S1_q_a[3]_clock_0, S1_q_a[3]_clock_1, , , , );
S1_q_a[3] = S1_q_a[3]_PORT_A_data_out[0];

--S1_q_b[3] is data_v:u31|altsyncram:altsyncram_component|altsyncram_8it:auto_generated|altsyncram_iab2:altsyncram1|q_b[3]
S1_q_b[3]_PORT_A_data_in = VCC;
S1_q_b[3]_PORT_A_data_in_reg = DFFE(S1_q_b[3]_PORT_A_data_in, S1_q_b[3]_clock_0, , , );
S1_q_b[3]_PORT_B_data_in = T1_ram_rom_data_reg[3];
S1_q_b[3]_PORT_B_data_in_reg = DFFE(S1_q_b[3]_PORT_B_data_in, S1_q_b[3]_clock_1, , , );
S1_q_b[3]_PORT_A_address = BUS(C1_s[8], C1_s[9], C1_s[10], C1_s[11], C1_s[12], C1_s[13], C1_s[14], C1_s[15]);
S1_q_b[3]_PORT_A_address_reg = DFFE(S1_q_b[3]_PORT_A_address, S1_q_b[3]_clock_0, , , );
S1_q_b[3]_PORT_B_address = BUS(T1_ram_rom_addr_reg[0], T1_ram_rom_addr_reg[1], T1_ram_rom_addr_reg[2], T1_ram_rom_addr_reg[3], T1_ram_rom_addr_reg[4], T1_ram_rom_addr_reg[5], T1_ram_rom_addr_reg[6], T1_ram_rom_addr_reg[7]);
S1_q_b[3]_PORT_B_address_reg = DFFE(S1_q_b[3]_PORT_B_address, S1_q_b[3]_clock_1, , , );
S1_q_b[3]_PORT_A_write_enable = GND;
S1_q_b[3]_PORT_A_write_enable_reg = DFFE(S1_q_b[3]_PORT_A_write_enable, S1_q_b[3]_clock_0, , , );