d_switch.vhd

多功能函数发生器

library ieee;
USE ieee.std_logic_1164.all;
entity d_switch is
port(sw_out: out std_logic_vector(7 downto 0);
     sw_in0,sw_in1,sw_in2,sw_in3: in std_logic_vector(7 downto 0);
     c_switch:in std_logic_vector(1 downto 0));
end d_switch;
architecture behav of d_switch is
begin
process(c_switch)
   begin
  case c_switch is
  when "00"=>sw_out<=sw_in0;
  when "01"=>sw_out<=sw_in1;
  when "10"=>sw_out<=sw_in2;
  when "11"=>sw_out<=sw_in3;
when others=> null;
end case;
end process;
end architecture behav;