dds.tan.rpt

多功能函数发生器

+---------------------------------------------+-------+---------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                      ; From                                                                                                                                 ; To                                                                                                                                  ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 6.871 ns                         ; f_c[2]                                                                                                                               ; adder:u1|s[15]                                                                                                                      ;                              ; clk                          ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 15.975 ns                        ; data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1|ram_block3a0~porta_address_reg7 ; s_out[3]                                                                                                                            ; clk                          ;                              ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 15.176 ns                        ; switch[1]                                                                                                                            ; s_out[3]                                                                                                                            ;                              ;                              ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 3.285 ns                         ; altera_internal_jtag                                                                                                                 ; data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]              ;                              ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 85.69 MHz ( period = 11.670 ns ) ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:4:IRF|Q[2]                                                                                   ; sld_hub:sld_hub_inst|hub_tdo                                                                                                        ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'clk'                          ; N/A   ; None          ; 197.01 MHz ( period = 5.076 ns ) ; data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1|ram_block3a0~porta_datain_reg0  ; data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1|ram_block3a0~porta_memory_reg0 ; clk                          ; clk                          ; 0            ;
; Total number of failed paths                ;       ;               ;                                  ;                                                                                                                                      ;                                                                                                                                     ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                          ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name              ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+