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📄 dds.fit.eqn

📁 多功能函数发生器
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--X1_q_a[4] is data_juchi:u33|altsyncram:altsyncram_component|altsyncram_7vt:auto_generated|altsyncram_fnb2:altsyncram1|q_a[4] at M4K_X13_Y7
X1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
X1_q_a[0]_PORT_A_data_in_reg = DFFE(X1_q_a[0]_PORT_A_data_in, X1_q_a[0]_clock_0, , , );
X1_q_a[0]_PORT_B_data_in = BUS(T3_ram_rom_data_reg[0], T3_ram_rom_data_reg[1], T3_ram_rom_data_reg[2], T3_ram_rom_data_reg[3], T3_ram_rom_data_reg[4], T3_ram_rom_data_reg[5], T3_ram_rom_data_reg[6], T3_ram_rom_data_reg[7]);
X1_q_a[0]_PORT_B_data_in_reg = DFFE(X1_q_a[0]_PORT_B_data_in, X1_q_a[0]_clock_1, , , );
X1_q_a[0]_PORT_A_address = BUS(C1_s[8], C1_s[9], C1_s[10], C1_s[11], C1_s[12], C1_s[13], C1_s[14], C1_s[15]);
X1_q_a[0]_PORT_A_address_reg = DFFE(X1_q_a[0]_PORT_A_address, X1_q_a[0]_clock_0, , , );
X1_q_a[0]_PORT_B_address = BUS(T3_ram_rom_addr_reg[0], T3_ram_rom_addr_reg[1], T3_ram_rom_addr_reg[2], T3_ram_rom_addr_reg[3], T3_ram_rom_addr_reg[4], T3_ram_rom_addr_reg[5], T3_ram_rom_addr_reg[6], T3_ram_rom_addr_reg[7]);
X1_q_a[0]_PORT_B_address_reg = DFFE(X1_q_a[0]_PORT_B_address, X1_q_a[0]_clock_1, , , );
X1_q_a[0]_PORT_A_write_enable = GND;
X1_q_a[0]_PORT_A_write_enable_reg = DFFE(X1_q_a[0]_PORT_A_write_enable, X1_q_a[0]_clock_0, , , );
X1_q_a[0]_PORT_B_write_enable = T3L2;
X1_q_a[0]_PORT_B_write_enable_reg = DFFE(X1_q_a[0]_PORT_B_write_enable, X1_q_a[0]_clock_1, , , );
X1_q_a[0]_clock_0 = GLOBAL(clk);
X1_q_a[0]_clock_1 = GLOBAL(A1L5);
X1_q_a[0]_PORT_A_data_out = MEMORY(X1_q_a[0]_PORT_A_data_in_reg, X1_q_a[0]_PORT_B_data_in_reg, X1_q_a[0]_PORT_A_address_reg, X1_q_a[0]_PORT_B_address_reg, X1_q_a[0]_PORT_A_write_enable_reg, X1_q_a[0]_PORT_B_write_enable_reg, , , X1_q_a[0]_clock_0, X1_q_a[0]_clock_1, , , , );
X1_q_a[4] = X1_q_a[0]_PORT_A_data_out[4];

--X1_q_a[3] is data_juchi:u33|altsyncram:altsyncram_component|altsyncram_7vt:auto_generated|altsyncram_fnb2:altsyncram1|q_a[3] at M4K_X13_Y7
X1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
X1_q_a[0]_PORT_A_data_in_reg = DFFE(X1_q_a[0]_PORT_A_data_in, X1_q_a[0]_clock_0, , , );
X1_q_a[0]_PORT_B_data_in = BUS(T3_ram_rom_data_reg[0], T3_ram_rom_data_reg[1], T3_ram_rom_data_reg[2], T3_ram_rom_data_reg[3], T3_ram_rom_data_reg[4], T3_ram_rom_data_reg[5], T3_ram_rom_data_reg[6], T3_ram_rom_data_reg[7]);
X1_q_a[0]_PORT_B_data_in_reg = DFFE(X1_q_a[0]_PORT_B_data_in, X1_q_a[0]_clock_1, , , );
X1_q_a[0]_PORT_A_address = BUS(C1_s[8], C1_s[9], C1_s[10], C1_s[11], C1_s[12], C1_s[13], C1_s[14], C1_s[15]);
X1_q_a[0]_PORT_A_address_reg = DFFE(X1_q_a[0]_PORT_A_address, X1_q_a[0]_clock_0, , , );
X1_q_a[0]_PORT_B_address = BUS(T3_ram_rom_addr_reg[0], T3_ram_rom_addr_reg[1], T3_ram_rom_addr_reg[2], T3_ram_rom_addr_reg[3], T3_ram_rom_addr_reg[4], T3_ram_rom_addr_reg[5], T3_ram_rom_addr_reg[6], T3_ram_rom_addr_reg[7]);
X1_q_a[0]_PORT_B_address_reg = DFFE(X1_q_a[0]_PORT_B_address, X1_q_a[0]_clock_1, , , );
X1_q_a[0]_PORT_A_write_enable = GND;
X1_q_a[0]_PORT_A_write_enable_reg = DFFE(X1_q_a[0]_PORT_A_write_enable, X1_q_a[0]_clock_0, , , );
X1_q_a[0]_PORT_B_write_enable = T3L2;
X1_q_a[0]_PORT_B_write_enable_reg = DFFE(X1_q_a[0]_PORT_B_write_enable, X1_q_a[0]_clock_1, , , );
X1_q_a[0]_clock_0 = GLOBAL(clk);
X1_q_a[0]_clock_1 = GLOBAL(A1L5);
X1_q_a[0]_PORT_A_data_out = MEMORY(X1_q_a[0]_PORT_A_data_in_reg, X1_q_a[0]_PORT_B_data_in_reg, X1_q_a[0]_PORT_A_address_reg, X1_q_a[0]_PORT_B_address_reg, X1_q_a[0]_PORT_A_write_enable_reg, X1_q_a[0]_PORT_B_write_enable_reg, , , X1_q_a[0]_clock_0, X1_q_a[0]_clock_1, , , , );
X1_q_a[3] = X1_q_a[0]_PORT_A_data_out[3];

--X1_q_a[2] is data_juchi:u33|altsyncram:altsyncram_component|altsyncram_7vt:auto_generated|altsyncram_fnb2:altsyncram1|q_a[2] at M4K_X13_Y7
X1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
X1_q_a[0]_PORT_A_data_in_reg = DFFE(X1_q_a[0]_PORT_A_data_in, X1_q_a[0]_clock_0, , , );
X1_q_a[0]_PORT_B_data_in = BUS(T3_ram_rom_data_reg[0], T3_ram_rom_data_reg[1], T3_ram_rom_data_reg[2], T3_ram_rom_data_reg[3], T3_ram_rom_data_reg[4], T3_ram_rom_data_reg[5], T3_ram_rom_data_reg[6], T3_ram_rom_data_reg[7]);
X1_q_a[0]_PORT_B_data_in_reg = DFFE(X1_q_a[0]_PORT_B_data_in, X1_q_a[0]_clock_1, , , );
X1_q_a[0]_PORT_A_address = BUS(C1_s[8], C1_s[9], C1_s[10], C1_s[11], C1_s[12], C1_s[13], C1_s[14], C1_s[15]);
X1_q_a[0]_PORT_A_address_reg = DFFE(X1_q_a[0]_PORT_A_address, X1_q_a[0]_clock_0, , , );
X1_q_a[0]_PORT_B_address = BUS(T3_ram_rom_addr_reg[0], T3_ram_rom_addr_reg[1], T3_ram_rom_addr_reg[2], T3_ram_rom_addr_reg[3], T3_ram_rom_addr_reg[4], T3_ram_rom_addr_reg[5], T3_ram_rom_addr_reg[6], T3_ram_rom_addr_reg[7]);
X1_q_a[0]_PORT_B_address_reg = DFFE(X1_q_a[0]_PORT_B_address, X1_q_a[0]_clock_1, , , );
X1_q_a[0]_PORT_A_write_enable = GND;
X1_q_a[0]_PORT_A_write_enable_reg = DFFE(X1_q_a[0]_PORT_A_write_enable, X1_q_a[0]_clock_0, , , );
X1_q_a[0]_PORT_B_write_enable = T3L2;
X1_q_a[0]_PORT_B_write_enable_reg = DFFE(X1_q_a[0]_PORT_B_write_enable, X1_q_a[0]_clock_1, , , );
X1_q_a[0]_clock_0 = GLOBAL(clk);
X1_q_a[0]_clock_1 = GLOBAL(A1L5);
X1_q_a[0]_PORT_A_data_out = MEMORY(X1_q_a[0]_PORT_A_data_in_reg, X1_q_a[0]_PORT_B_data_in_reg, X1_q_a[0]_PORT_A_address_reg, X1_q_a[0]_PORT_B_address_reg, X1_q_a[0]_PORT_A_write_enable_reg, X1_q_a[0]_PORT_B_write_enable_reg, , , X1_q_a[0]_clock_0, X1_q_a[0]_clock_1, , , , );
X1_q_a[2] = X1_q_a[0]_PORT_A_data_out[2];

--X1_q_a[1] is data_juchi:u33|altsyncram:altsyncram_component|altsyncram_7vt:auto_generated|altsyncram_fnb2:altsyncram1|q_a[1] at M4K_X13_Y7
X1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
X1_q_a[0]_PORT_A_data_in_reg = DFFE(X1_q_a[0]_PORT_A_data_in, X1_q_a[0]_clock_0, , , );
X1_q_a[0]_PORT_B_data_in = BUS(T3_ram_rom_data_reg[0], T3_ram_rom_data_reg[1], T3_ram_rom_data_reg[2], T3_ram_rom_data_reg[3], T3_ram_rom_data_reg[4], T3_ram_rom_data_reg[5], T3_ram_rom_data_reg[6], T3_ram_rom_data_reg[7]);
X1_q_a[0]_PORT_B_data_in_reg = DFFE(X1_q_a[0]_PORT_B_data_in, X1_q_a[0]_clock_1, , , );
X1_q_a[0]_PORT_A_address = BUS(C1_s[8], C1_s[9], C1_s[10], C1_s[11], C1_s[12], C1_s[13], C1_s[14], C1_s[15]);
X1_q_a[0]_PORT_A_address_reg = DFFE(X1_q_a[0]_PORT_A_address, X1_q_a[0]_clock_0, , , );
X1_q_a[0]_PORT_B_address = BUS(T3_ram_rom_addr_reg[0], T3_ram_rom_addr_reg[1], T3_ram_rom_addr_reg[2], T3_ram_rom_addr_reg[3], T3_ram_rom_addr_reg[4], T3_ram_rom_addr_reg[5], T3_ram_rom_addr_reg[6], T3_ram_rom_addr_reg[7]);
X1_q_a[0]_PORT_B_address_reg = DFFE(X1_q_a[0]_PORT_B_address, X1_q_a[0]_clock_1, , , );
X1_q_a[0]_PORT_A_write_enable = GND;
X1_q_a[0]_PORT_A_write_enable_reg = DFFE(X1_q_a[0]_PORT_A_write_enable, X1_q_a[0]_clock_0, , , );
X1_q_a[0]_PORT_B_write_enable = T3L2;
X1_q_a[0]_PORT_B_write_enable_reg = DFFE(X1_q_a[0]_PORT_B_write_enable, X1_q_a[0]_clock_1, , , );
X1_q_a[0]_clock_0 = GLOBAL(clk);
X1_q_a[0]_clock_1 = GLOBAL(A1L5);
X1_q_a[0]_PORT_A_data_out = MEMORY(X1_q_a[0]_PORT_A_data_in_reg, X1_q_a[0]_PORT_B_data_in_reg, X1_q_a[0]_PORT_A_address_reg, X1_q_a[0]_PORT_B_address_reg, X1_q_a[0]_PORT_A_write_enable_reg, X1_q_a[0]_PORT_B_write_enable_reg, , , X1_q_a[0]_clock_0, X1_q_a[0]_clock_1, , , , );
X1_q_a[1] = X1_q_a[0]_PORT_A_data_out[1];

--X1_q_b[7] is data_juchi:u33|altsyncram:altsyncram_component|altsyncram_7vt:auto_generated|altsyncram_fnb2:altsyncram1|q_b[7] at M4K_X13_Y7
X1_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
X1_q_b[0]_PORT_A_data_in_reg = DFFE(X1_q_b[0]_PORT_A_data_in, X1_q_b[0]_clock_0, , , );
X1_q_b[0]_PORT_B_data_in = BUS(T3_ram_rom_data_reg[0], T3_ram_rom_data_reg[1], T3_ram_rom_data_reg[2], T3_ram_rom_data_reg[3], T3_ram_rom_data_reg[4], T3_ram_rom_data_reg[5], T3_ram_rom_data_reg[6], T3_ram_rom_data_reg[7]);
X1_q_b[0]_PORT_B_data_in_reg = DFFE(X1_q_b[0]_PORT_B_data_in, X1_q_b[0]_clock_1, , , );
X1_q_b[0]_PORT_A_address = BUS(C1_s[8], C1_s[9], C1_s[10], C1_s[11], C1_s[12], C1_s[13], C1_s[14], C1_s[15]);
X1_q_b[0]_PORT_A_address_reg = DFFE(X1_q_b[0]_PORT_A_address, X1_q_b[0]_clock_0, , , );
X1_q_b[0]_PORT_B_address = BUS(T3_ram_rom_addr_reg[0], T3_ram_rom_addr_reg[1], T3_ram_rom_addr_reg[2], T3_ram_rom_addr_reg[3], T3_ram_rom_addr_reg[4], T3_ram_rom_addr_reg[5], T3_ram_rom_addr_reg[6], T3_ram_rom_addr_reg[7]);
X1_q_b[0]_PORT_B_address_reg = DFFE(X1_q_b[0]_PORT_B_address, X1_q_b[0]_clock_1, , , );
X1_q_b[0]_PORT_A_write_enable = GND;
X1_q_b[0]_PORT_A_write_enable_reg = DFFE(X1_q_b[0]_PORT_A_write_enable, X1_q_b[0]_clock_0, , , );
X1_q_b[0]_PORT_B_write_enable = T3L2;
X1_q_b[0]_PORT_B_write_enable_reg = DFFE(X1_q_b[0]_PORT_B_write_enable, X1_q_b[0]_clock_1, , , );
X1_q_b[0]_clock_0 = GLOBAL(clk);
X1_q_b[0]_clock_1 = GLOBAL(A1L5);
X1_q_b[0]_PORT_B_data_out = MEMORY(X1_q_b[0]_PORT_A_data_in_reg, X1_q_b[0]_PORT_B_data_in_reg, X1_q_b[0]_PORT_A_address_reg, X1_q_b[0]_PORT_B_address_reg, X1_q_b[0]_PORT_A_write_enable_reg, X1_q_b[0]_PORT_B_write_enable_reg, , , X1_q_b[0]_clock_0, X1_q_b[0]_clock_1, , , , );
X1_q_b[7] = X1_q_b[0]_PORT_B_data_out[7];

--X1_q_b[6] is data_juchi:u33|altsyncram:altsyncram_component|altsyncram_7vt:auto_generated|altsyncram_fnb2:altsyncram1|q_b[6] at M4K_X13_Y7
X1_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
X1_q_b[0]_PORT_A_data_in_reg = DFFE(X1_q_b[0]_PORT_A_data_in, X1_q_b[0]_clock_0, , , );
X1_q_b[0]_PORT_B_data_in = BUS(T3_ram_rom_data_reg[0], T3_ram_rom_data_reg[1], T3_ram_rom_data_reg[2], T3_ram_rom_data_reg[3], T3_ram_rom_data_reg[4], T3_ram_rom_data_reg[5], T3_ram_rom_data_reg[6], T3_ram_rom_data_reg[7]);
X1_q_b[0]_PORT_B_data_in_reg = DFFE(X1_q_b[0]_PORT_B_data_in, X1_q_b[0]_clock_1, , , );
X1_q_b[0]_PORT_A_address = BUS(C1_s[8], C1_s[9], C1_s[10], C1_s[11], C1_s[12], C1_s[13], C1_s[14], C1_s[15]);
X1_q_b[0]_PORT_A_address_reg = DFFE(X1_q_b[0]_PORT_A_address, X1_q_b[0]_clock_0, , , );
X1_q_b[0]_PORT_B_address = BUS(T3_ram_rom_addr_reg[0], T3_ram_rom_addr_reg[1], T3_ram_rom_addr_reg[2], T3_ram_rom_addr_reg[3], T3_ram_rom_addr_reg[4], T3_ram_rom_addr_reg[5], T3_ram_rom_addr_reg[6], T3_ram_rom_addr_reg[7]);
X1_q_b[0]_PORT_B_address_reg = DFFE(X1_q_b[0]_PORT_B_address, X1_q_b[0]_clock_1, , , );
X1_q_b[0]_PORT_A_write_enable = GND;
X1_q_b[0]_PORT_A_write_enable_reg = DFFE(X1_q_b[0]_PORT_A_write_enable, X1_q_b[0]_clock_0, , , );
X1_q_b[0]_PORT_B_write_enable = T3L2;
X1_q_b[0]_PORT_B_write_enable_reg = DFFE(X1_q_b[0]_PORT_B_write_enable, X1_q_b[0]_clock_1, , , );
X1_q_b[0]_clock_0 = GLOBAL(clk);
X1_q_b[0]_clock_1 = GLOBAL(A1L5);
X1_q_b[0]_PORT_B_data_out = MEMORY(X1_q_b[0]_PORT_A_data_in_reg, X1_q_b[0]_PORT_B_data_in_reg, X1_q_b[0]_PORT_A_address_reg, X1_q_b[0]_PORT_B_address_reg, X1_q_b[0]_PORT_A_write_enable_reg, X1_q_b[0]_PORT_B_write_enable_reg, , , X1_q_b[0]_clock_0, X1_q_b[0]_clock_1, , , , );
X1_q_b[6] = X1_q_b[0]_PORT_B_data_out[6];

--X1_q_b[5] is data_juchi:u33|altsyncram:altsyncram_component|altsyncram_7vt:auto_generated|altsyncram_fnb2:altsyncram1|q_b[5] at M4K_X13_Y7
X1_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
X1_q_b[0]_PORT_A_data_in_reg = DFFE(X1_q_b[0]_PORT_A_data_in, X1_q_b[0]_clock_0, , , );
X1_q_b[0]_PORT_B_data_in = BUS(T3_ram_rom_data_reg[0], T3_ram_rom_data_reg[1], T3_ram_rom_data_reg[2], T3_ram_rom_data_reg[3], T3_ram_rom_data_reg[4], T3_ram_rom_data_reg[5], T3_ram_rom_data_reg[6], T3_ram_rom_data_reg[7]);
X1_q_b[0]_PORT_B_data_in_reg = DFFE(X1_q_b[0]_PORT_B_data_in, X1_q_b[0]_clock_1, , , );
X1_q_b[0]_PORT_A_address = BUS(C1_s[8], C1_s[9], C1_s[10], C1_s[11], C1_s[12], C1_s[13], C1_s[14], C1_s[15]);
X1_q_b[0]_PORT_A_address_reg = DFFE(X1_q_b[0]_PORT_A_address, X1_q_b[0]_clock_0, , , );
X1_q_b[0]_PORT_B_address = BUS(T3_ram_rom_addr_reg[0], T3_ram_rom_addr_reg[1], T3_ram_rom_addr_reg[2], T3_ram_rom_addr_reg[3], T3_ram_rom_addr_reg[4], T3_ram_rom_addr_reg[5], T3_ram_rom_addr_reg[6], T3_ram_rom_addr_reg[7]);
X1_q_b[0]_PORT_B_address_reg = DFFE(X1_q_b[0]_PORT_B_address, X1_q_b[0]_clock_1, , , );
X1_q_b[0]_PORT_A_write_enable = GND;
X1_q_b[0]_PORT_A_write_enable_reg = DFFE(X1_q_b[0]_PORT_A_write_enable, X1_q_b[0]_clock_0, , , );
X1_q_b[0]_PORT_B_write_enable = T3L2;
X1_q_b[0]_PORT_B_write_enable_reg = DFFE(X1_q_b[0]_PORT_B_write_enable, X1_q_b[0]_clock_1, , , );
X1_q_b[0]_clock_0 = GLOBAL(clk);
X1_q_b[0]_clock_1 = GLOBAL(A1L5);
X1_q_b[0]_PORT_B_data_out = MEMORY(X1_q_b[0]_PORT_A_data_in_reg, X1_q_b[0]_PORT_B_data_in_reg, X1_q_b[0]_PORT_A_address_reg, X1_q_b[0]_PORT_B_address_reg, X1_q_b[0]_PORT_A_write_enable_reg, X1_q_b[0]_PORT_B_write_enable_reg, , , X1_q_b[0]_clock_0, X1_q_b[0]_clock_1, , , , );
X1_q_b[5] = X1_q_b[0]_PORT_B_data_out[5];

--X1_q_b[4] is data_juchi:u33|altsyncram:altsyncram_component|altsyncram_7vt:auto_generated|altsyncram_fnb2:altsyncram1|q_b[4] at M4K_X13_Y7
X1_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
X1_q_b[0]_PORT_A_data_in_reg = DFFE(X1_q_b[0]_PORT_A_data_in, X1_q_b[0]_clock_0, , , );
X1_q_b[0]_PORT_B_data_in = BUS(T3_ram_rom_data_reg[0], T3_ram_rom_data_reg[1], T3_ram_rom_data_reg[2], T3_ram_rom_data_reg[3], T3_ram_rom_data_reg[4], T3_ram_rom_data_reg[5], T3_ram_rom_data_reg[6], T3_ram_rom_data_reg[7]);
X1_q_b[0]_PORT_B_data_in_reg = DFFE(X1_q_b[0]_PORT_B_data_in, X1_q_b[0]_clock_1, , , );
X1_q_b[0]_PORT_A_address = BUS(C1_s[8], C1_s[9], C1_s[10], C1_s[11], C1_s[12], C1_s[13], C1_s[14], C1_s[15]);
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