dds.fit.eqn

多功能函数发生器

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--V1_q_a[0] is data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1|q_a[0] at M4K_X13_Y9
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 8, Port B Depth: 256, Port B Width: 8
--Port A Logical Depth: 256, Port A Logical Width: 8, Port B Logical Depth: 256, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
V1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
V1_q_a[0]_PORT_A_data_in_reg = DFFE(V1_q_a[0]_PORT_A_data_in, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_data_in = BUS(T2_ram_rom_data_reg[0], T2_ram_rom_data_reg[1], T2_ram_rom_data_reg[2], T2_ram_rom_data_reg[3], T2_ram_rom_data_reg[4], T2_ram_rom_data_reg[5], T2_ram_rom_data_reg[6], T2_ram_rom_data_reg[7]);
V1_q_a[0]_PORT_B_data_in_reg = DFFE(V1_q_a[0]_PORT_B_data_in, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_PORT_A_address = BUS(C1_s[8], C1_s[9], C1_s[10], C1_s[11], C1_s[12], C1_s[13], C1_s[14], C1_s[15]);
V1_q_a[0]_PORT_A_address_reg = DFFE(V1_q_a[0]_PORT_A_address, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_address = BUS(T2_ram_rom_addr_reg[0], T2_ram_rom_addr_reg[1], T2_ram_rom_addr_reg[2], T2_ram_rom_addr_reg[3], T2_ram_rom_addr_reg[4], T2_ram_rom_addr_reg[5], T2_ram_rom_addr_reg[6], T2_ram_rom_addr_reg[7]);
V1_q_a[0]_PORT_B_address_reg = DFFE(V1_q_a[0]_PORT_B_address, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_PORT_A_write_enable = GND;
V1_q_a[0]_PORT_A_write_enable_reg = DFFE(V1_q_a[0]_PORT_A_write_enable, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_write_enable = T2L2;
V1_q_a[0]_PORT_B_write_enable_reg = DFFE(V1_q_a[0]_PORT_B_write_enable, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_clock_0 = GLOBAL(clk);
V1_q_a[0]_clock_1 = GLOBAL(A1L5);
V1_q_a[0]_PORT_A_data_out = MEMORY(V1_q_a[0]_PORT_A_data_in_reg, V1_q_a[0]_PORT_B_data_in_reg, V1_q_a[0]_PORT_A_address_reg, V1_q_a[0]_PORT_B_address_reg, V1_q_a[0]_PORT_A_write_enable_reg, V1_q_a[0]_PORT_B_write_enable_reg, , , V1_q_a[0]_clock_0, V1_q_a[0]_clock_1, , , , );
V1_q_a[0] = V1_q_a[0]_PORT_A_data_out[0];

--V1_q_b[0] is data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1|q_b[0] at M4K_X13_Y9
V1_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
V1_q_b[0]_PORT_A_data_in_reg = DFFE(V1_q_b[0]_PORT_A_data_in, V1_q_b[0]_clock_0, , , );
V1_q_b[0]_PORT_B_data_in = BUS(T2_ram_rom_data_reg[0], T2_ram_rom_data_reg[1], T2_ram_rom_data_reg[2], T2_ram_rom_data_reg[3], T2_ram_rom_data_reg[4], T2_ram_rom_data_reg[5], T2_ram_rom_data_reg[6], T2_ram_rom_data_reg[7]);
V1_q_b[0]_PORT_B_data_in_reg = DFFE(V1_q_b[0]_PORT_B_data_in, V1_q_b[0]_clock_1, , , );
V1_q_b[0]_PORT_A_address = BUS(C1_s[8], C1_s[9], C1_s[10], C1_s[11], C1_s[12], C1_s[13], C1_s[14], C1_s[15]);
V1_q_b[0]_PORT_A_address_reg = DFFE(V1_q_b[0]_PORT_A_address, V1_q_b[0]_clock_0, , , );
V1_q_b[0]_PORT_B_address = BUS(T2_ram_rom_addr_reg[0], T2_ram_rom_addr_reg[1], T2_ram_rom_addr_reg[2], T2_ram_rom_addr_reg[3], T2_ram_rom_addr_reg[4], T2_ram_rom_addr_reg[5], T2_ram_rom_addr_reg[6], T2_ram_rom_addr_reg[7]);
V1_q_b[0]_PORT_B_address_reg = DFFE(V1_q_b[0]_PORT_B_address, V1_q_b[0]_clock_1, , , );
V1_q_b[0]_PORT_A_write_enable = GND;
V1_q_b[0]_PORT_A_write_enable_reg = DFFE(V1_q_b[0]_PORT_A_write_enable, V1_q_b[0]_clock_0, , , );
V1_q_b[0]_PORT_B_write_enable = T2L2;
V1_q_b[0]_PORT_B_write_enable_reg = DFFE(V1_q_b[0]_PORT_B_write_enable, V1_q_b[0]_clock_1, , , );
V1_q_b[0]_clock_0 = GLOBAL(clk);
V1_q_b[0]_clock_1 = GLOBAL(A1L5);
V1_q_b[0]_PORT_B_data_out = MEMORY(V1_q_b[0]_PORT_A_data_in_reg, V1_q_b[0]_PORT_B_data_in_reg, V1_q_b[0]_PORT_A_address_reg, V1_q_b[0]_PORT_B_address_reg, V1_q_b[0]_PORT_A_write_enable_reg, V1_q_b[0]_PORT_B_write_enable_reg, , , V1_q_b[0]_clock_0, V1_q_b[0]_clock_1, , , , );
V1_q_b[0] = V1_q_b[0]_PORT_B_data_out[0];

--V1_q_a[7] is data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1|q_a[7] at M4K_X13_Y9
V1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
V1_q_a[0]_PORT_A_data_in_reg = DFFE(V1_q_a[0]_PORT_A_data_in, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_data_in = BUS(T2_ram_rom_data_reg[0], T2_ram_rom_data_reg[1], T2_ram_rom_data_reg[2], T2_ram_rom_data_reg[3], T2_ram_rom_data_reg[4], T2_ram_rom_data_reg[5], T2_ram_rom_data_reg[6], T2_ram_rom_data_reg[7]);
V1_q_a[0]_PORT_B_data_in_reg = DFFE(V1_q_a[0]_PORT_B_data_in, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_PORT_A_address = BUS(C1_s[8], C1_s[9], C1_s[10], C1_s[11], C1_s[12], C1_s[13], C1_s[14], C1_s[15]);
V1_q_a[0]_PORT_A_address_reg = DFFE(V1_q_a[0]_PORT_A_address, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_address = BUS(T2_ram_rom_addr_reg[0], T2_ram_rom_addr_reg[1], T2_ram_rom_addr_reg[2], T2_ram_rom_addr_reg[3], T2_ram_rom_addr_reg[4], T2_ram_rom_addr_reg[5], T2_ram_rom_addr_reg[6], T2_ram_rom_addr_reg[7]);
V1_q_a[0]_PORT_B_address_reg = DFFE(V1_q_a[0]_PORT_B_address, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_PORT_A_write_enable = GND;
V1_q_a[0]_PORT_A_write_enable_reg = DFFE(V1_q_a[0]_PORT_A_write_enable, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_write_enable = T2L2;
V1_q_a[0]_PORT_B_write_enable_reg = DFFE(V1_q_a[0]_PORT_B_write_enable, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_clock_0 = GLOBAL(clk);
V1_q_a[0]_clock_1 = GLOBAL(A1L5);
V1_q_a[0]_PORT_A_data_out = MEMORY(V1_q_a[0]_PORT_A_data_in_reg, V1_q_a[0]_PORT_B_data_in_reg, V1_q_a[0]_PORT_A_address_reg, V1_q_a[0]_PORT_B_address_reg, V1_q_a[0]_PORT_A_write_enable_reg, V1_q_a[0]_PORT_B_write_enable_reg, , , V1_q_a[0]_clock_0, V1_q_a[0]_clock_1, , , , );
V1_q_a[7] = V1_q_a[0]_PORT_A_data_out[7];

--V1_q_a[6] is data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1|q_a[6] at M4K_X13_Y9
V1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
V1_q_a[0]_PORT_A_data_in_reg = DFFE(V1_q_a[0]_PORT_A_data_in, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_data_in = BUS(T2_ram_rom_data_reg[0], T2_ram_rom_data_reg[1], T2_ram_rom_data_reg[2], T2_ram_rom_data_reg[3], T2_ram_rom_data_reg[4], T2_ram_rom_data_reg[5], T2_ram_rom_data_reg[6], T2_ram_rom_data_reg[7]);
V1_q_a[0]_PORT_B_data_in_reg = DFFE(V1_q_a[0]_PORT_B_data_in, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_PORT_A_address = BUS(C1_s[8], C1_s[9], C1_s[10], C1_s[11], C1_s[12], C1_s[13], C1_s[14], C1_s[15]);
V1_q_a[0]_PORT_A_address_reg = DFFE(V1_q_a[0]_PORT_A_address, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_address = BUS(T2_ram_rom_addr_reg[0], T2_ram_rom_addr_reg[1], T2_ram_rom_addr_reg[2], T2_ram_rom_addr_reg[3], T2_ram_rom_addr_reg[4], T2_ram_rom_addr_reg[5], T2_ram_rom_addr_reg[6], T2_ram_rom_addr_reg[7]);
V1_q_a[0]_PORT_B_address_reg = DFFE(V1_q_a[0]_PORT_B_address, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_PORT_A_write_enable = GND;
V1_q_a[0]_PORT_A_write_enable_reg = DFFE(V1_q_a[0]_PORT_A_write_enable, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_write_enable = T2L2;
V1_q_a[0]_PORT_B_write_enable_reg = DFFE(V1_q_a[0]_PORT_B_write_enable, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_clock_0 = GLOBAL(clk);
V1_q_a[0]_clock_1 = GLOBAL(A1L5);
V1_q_a[0]_PORT_A_data_out = MEMORY(V1_q_a[0]_PORT_A_data_in_reg, V1_q_a[0]_PORT_B_data_in_reg, V1_q_a[0]_PORT_A_address_reg, V1_q_a[0]_PORT_B_address_reg, V1_q_a[0]_PORT_A_write_enable_reg, V1_q_a[0]_PORT_B_write_enable_reg, , , V1_q_a[0]_clock_0, V1_q_a[0]_clock_1, , , , );
V1_q_a[6] = V1_q_a[0]_PORT_A_data_out[6];

--V1_q_a[5] is data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1|q_a[5] at M4K_X13_Y9
V1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
V1_q_a[0]_PORT_A_data_in_reg = DFFE(V1_q_a[0]_PORT_A_data_in, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_data_in = BUS(T2_ram_rom_data_reg[0], T2_ram_rom_data_reg[1], T2_ram_rom_data_reg[2], T2_ram_rom_data_reg[3], T2_ram_rom_data_reg[4], T2_ram_rom_data_reg[5], T2_ram_rom_data_reg[6], T2_ram_rom_data_reg[7]);
V1_q_a[0]_PORT_B_data_in_reg = DFFE(V1_q_a[0]_PORT_B_data_in, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_PORT_A_address = BUS(C1_s[8], C1_s[9], C1_s[10], C1_s[11], C1_s[12], C1_s[13], C1_s[14], C1_s[15]);
V1_q_a[0]_PORT_A_address_reg = DFFE(V1_q_a[0]_PORT_A_address, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_address = BUS(T2_ram_rom_addr_reg[0], T2_ram_rom_addr_reg[1], T2_ram_rom_addr_reg[2], T2_ram_rom_addr_reg[3], T2_ram_rom_addr_reg[4], T2_ram_rom_addr_reg[5], T2_ram_rom_addr_reg[6], T2_ram_rom_addr_reg[7]);
V1_q_a[0]_PORT_B_address_reg = DFFE(V1_q_a[0]_PORT_B_address, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_PORT_A_write_enable = GND;
V1_q_a[0]_PORT_A_write_enable_reg = DFFE(V1_q_a[0]_PORT_A_write_enable, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_write_enable = T2L2;
V1_q_a[0]_PORT_B_write_enable_reg = DFFE(V1_q_a[0]_PORT_B_write_enable, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_clock_0 = GLOBAL(clk);
V1_q_a[0]_clock_1 = GLOBAL(A1L5);
V1_q_a[0]_PORT_A_data_out = MEMORY(V1_q_a[0]_PORT_A_data_in_reg, V1_q_a[0]_PORT_B_data_in_reg, V1_q_a[0]_PORT_A_address_reg, V1_q_a[0]_PORT_B_address_reg, V1_q_a[0]_PORT_A_write_enable_reg, V1_q_a[0]_PORT_B_write_enable_reg, , , V1_q_a[0]_clock_0, V1_q_a[0]_clock_1, , , , );
V1_q_a[5] = V1_q_a[0]_PORT_A_data_out[5];

--V1_q_a[4] is data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1|q_a[4] at M4K_X13_Y9
V1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
V1_q_a[0]_PORT_A_data_in_reg = DFFE(V1_q_a[0]_PORT_A_data_in, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_data_in = BUS(T2_ram_rom_data_reg[0], T2_ram_rom_data_reg[1], T2_ram_rom_data_reg[2], T2_ram_rom_data_reg[3], T2_ram_rom_data_reg[4], T2_ram_rom_data_reg[5], T2_ram_rom_data_reg[6], T2_ram_rom_data_reg[7]);
V1_q_a[0]_PORT_B_data_in_reg = DFFE(V1_q_a[0]_PORT_B_data_in, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_PORT_A_address = BUS(C1_s[8], C1_s[9], C1_s[10], C1_s[11], C1_s[12], C1_s[13], C1_s[14], C1_s[15]);
V1_q_a[0]_PORT_A_address_reg = DFFE(V1_q_a[0]_PORT_A_address, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_address = BUS(T2_ram_rom_addr_reg[0], T2_ram_rom_addr_reg[1], T2_ram_rom_addr_reg[2], T2_ram_rom_addr_reg[3], T2_ram_rom_addr_reg[4], T2_ram_rom_addr_reg[5], T2_ram_rom_addr_reg[6], T2_ram_rom_addr_reg[7]);
V1_q_a[0]_PORT_B_address_reg = DFFE(V1_q_a[0]_PORT_B_address, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_PORT_A_write_enable = GND;
V1_q_a[0]_PORT_A_write_enable_reg = DFFE(V1_q_a[0]_PORT_A_write_enable, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_write_enable = T2L2;
V1_q_a[0]_PORT_B_write_enable_reg = DFFE(V1_q_a[0]_PORT_B_write_enable, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_clock_0 = GLOBAL(clk);
V1_q_a[0]_clock_1 = GLOBAL(A1L5);
V1_q_a[0]_PORT_A_data_out = MEMORY(V1_q_a[0]_PORT_A_data_in_reg, V1_q_a[0]_PORT_B_data_in_reg, V1_q_a[0]_PORT_A_address_reg, V1_q_a[0]_PORT_B_address_reg, V1_q_a[0]_PORT_A_write_enable_reg, V1_q_a[0]_PORT_B_write_enable_reg, , , V1_q_a[0]_clock_0, V1_q_a[0]_clock_1, , , , );
V1_q_a[4] = V1_q_a[0]_PORT_A_data_out[4];

--V1_q_a[3] is data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|altsyncram_2ab2:altsyncram1|q_a[3] at M4K_X13_Y9
V1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
V1_q_a[0]_PORT_A_data_in_reg = DFFE(V1_q_a[0]_PORT_A_data_in, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_data_in = BUS(T2_ram_rom_data_reg[0], T2_ram_rom_data_reg[1], T2_ram_rom_data_reg[2], T2_ram_rom_data_reg[3], T2_ram_rom_data_reg[4], T2_ram_rom_data_reg[5], T2_ram_rom_data_reg[6], T2_ram_rom_data_reg[7]);
V1_q_a[0]_PORT_B_data_in_reg = DFFE(V1_q_a[0]_PORT_B_data_in, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_PORT_A_address = BUS(C1_s[8], C1_s[9], C1_s[10], C1_s[11], C1_s[12], C1_s[13], C1_s[14], C1_s[15]);
V1_q_a[0]_PORT_A_address_reg = DFFE(V1_q_a[0]_PORT_A_address, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_address = BUS(T2_ram_rom_addr_reg[0], T2_ram_rom_addr_reg[1], T2_ram_rom_addr_reg[2], T2_ram_rom_addr_reg[3], T2_ram_rom_addr_reg[4], T2_ram_rom_addr_reg[5], T2_ram_rom_addr_reg[6], T2_ram_rom_addr_reg[7]);