dds.map.rpt

多功能函数发生器

Analysis & Synthesis report for dds
Sat Jul 19 17:19:51 2008
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. General Register Statistics
  9. Inverted Register Statistics
 10. Multiplexer Restructuring Statistics (Restructuring Performed)
 11. Parameter Settings for User Entity Instance: data_v:u31|altsyncram:altsyncram_component
 12. Parameter Settings for User Entity Instance: data_v:u31|altsyncram:altsyncram_component|altsyncram_8it:auto_generated|sld_mod_ram_rom:mgl_prim2
 13. Parameter Settings for User Entity Instance: data_f:u32|altsyncram:altsyncram_component
 14. Parameter Settings for User Entity Instance: data_f:u32|altsyncram:altsyncram_component|altsyncram_pht:auto_generated|sld_mod_ram_rom:mgl_prim2
 15. Parameter Settings for User Entity Instance: data_juchi:u33|altsyncram:altsyncram_component
 16. Parameter Settings for User Entity Instance: data_juchi:u33|altsyncram:altsyncram_component|altsyncram_7vt:auto_generated|sld_mod_ram_rom:mgl_prim2
 17. Parameter Settings for User Entity Instance: data_sin:u34|altsyncram:altsyncram_component
 18. Parameter Settings for User Entity Instance: data_sin:u34|altsyncram:altsyncram_component|altsyncram_rot:auto_generated|sld_mod_ram_rom:mgl_prim2
 19. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 20. In-System Memory Content Editor Settings
 21. Analysis & Synthesis Equations
 22. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sat Jul 19 17:19:51 2008    ;
; Quartus II Version          ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name               ; dds                                      ;
; Top-level Entity Name       ; dds                                      ;
; Family                      ; Cyclone                                  ;
; Total logic elements        ; 464                                      ;
; Total pins                  ; 21                                       ;
; Total virtual pins          ; 0                                        ;
; Total memory bits           ; 8,192                                    ;
; Total PLLs                  ; 0                                        ;
+-----------------------------+------------------------------------------+


+---------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                     ;
+--------------------------------------------------------------------+--------------+---------------+
; Option                                                             ; Setting      ; Default Value ;
+--------------------------------------------------------------------+--------------+---------------+
; Device                                                             ; EP1C3T144C8  ;               ;
; Top-level entity name                                              ; dds          ; dds           ;
; Family name                                                        ; Cyclone      ; Stratix       ;
; Use smart compilation                                              ; Off          ; Off           ;
; Restructure Multiplexers                                           ; Auto         ; Auto          ;
; Create Debugging Nodes for IP Cores                                ; off          ; off           ;
; Preserve fewer node names                                          ; On           ; On            ;
; Disable OpenCore Plus hardware evaluation                          ; Off          ; Off           ;
; Verilog Version                                                    ; Verilog_2001 ; Verilog_2001  ;
; VHDL Version                                                       ; VHDL93       ; VHDL93        ;
; State Machine Processing                                           ; Auto         ; Auto          ;
; Extract Verilog State Machines                                     ; On           ; On            ;
; Extract VHDL State Machines                                        ; On           ; On            ;
; Add Pass-Through Logic to Inferred RAMs                            ; On           ; On            ;
; NOT Gate Push-Back                                                 ; On           ; On            ;
; Power-Up Don't Care                                                ; On           ; On            ;
; Remove Redundant Logic Cells                                       ; Off          ; Off           ;
; Remove Duplicate Registers                                         ; On           ; On            ;
; Ignore CARRY Buffers                                               ; Off          ; Off           ;
; Ignore CASCADE Buffers                                             ; Off          ; Off           ;
; Ignore GLOBAL Buffers                                              ; Off          ; Off           ;
; Ignore ROW GLOBAL Buffers                                          ; Off          ; Off           ;
; Ignore LCELL Buffers                                               ; Off          ; Off           ;
; Ignore SOFT Buffers                                                ; On           ; On            ;
; Limit AHDL Integers to 32 Bits                                     ; Off          ; Off           ;
; Optimization Technique -- Cyclone                                  ; Balanced     ; Balanced      ;