📄 at91sam7se32.h
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// *****************************************************************************
// SOFTWARE API DEFINITION FOR Embedded Flash Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_EFC {
AT91_REG EFC_FMR; // MC Flash Mode Register
AT91_REG EFC_FCR; // MC Flash Command Register
AT91_REG EFC_FSR; // MC Flash Status Register
AT91_REG EFC_VR; // MC Flash Version Register
} AT91S_EFC, *AT91PS_EFC;
#else
#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_FMR) MC Flash Mode Register
#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_FCR) MC Flash Command Register
#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_FSR) MC Flash Status Register
#define MC_VR (AT91_CAST(AT91_REG *) 0x0000000C) // (MC_VR) MC Flash Version Register
#endif
// -------- MC_FMR : (EFC Offset: 0x0) MC Flash Mode Register --------
#define AT91C_MC_FRDY (0x1 << 0) // (EFC) Flash Ready
#define AT91C_MC_LOCKE (0x1 << 2) // (EFC) Lock Error
#define AT91C_MC_PROGE (0x1 << 3) // (EFC) Programming Error
#define AT91C_MC_NEBP (0x1 << 7) // (EFC) No Erase Before Programming
#define AT91C_MC_FWS (0x3 << 8) // (EFC) Flash Wait State
#define AT91C_MC_FWS_0FWS (0x0 << 8) // (EFC) 1 cycle for Read, 2 for Write operations
#define AT91C_MC_FWS_1FWS (0x1 << 8) // (EFC) 2 cycles for Read, 3 for Write operations
#define AT91C_MC_FWS_2FWS (0x2 << 8) // (EFC) 3 cycles for Read, 4 for Write operations
#define AT91C_MC_FWS_3FWS (0x3 << 8) // (EFC) 4 cycles for Read, 4 for Write operations
#define AT91C_MC_FMCN (0xFF << 16) // (EFC) Flash Microsecond Cycle Number
// -------- MC_FCR : (EFC Offset: 0x4) MC Flash Command Register --------
#define AT91C_MC_FCMD (0xF << 0) // (EFC) Flash Command
#define AT91C_MC_FCMD_START_PROG (0x1) // (EFC) Starts the programming of th epage specified by PAGEN.
#define AT91C_MC_FCMD_LOCK (0x2) // (EFC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (EFC) The lock sequence automatically happens after the programming sequence is completed.
#define AT91C_MC_FCMD_UNLOCK (0x4) // (EFC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (EFC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (EFC) Set General Purpose NVM bits.
#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (EFC) Clear General Purpose NVM bits.
#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (EFC) Set Security Bit.
#define AT91C_MC_PAGEN (0x3FF << 8) // (EFC) Page Number
#define AT91C_MC_KEY (0xFF << 24) // (EFC) Writing Protect Key
// -------- MC_FSR : (EFC Offset: 0x8) MC Flash Command Register --------
#define AT91C_MC_SECURITY (0x1 << 4) // (EFC) Security Bit Status
#define AT91C_MC_GPNVM0 (0x1 << 8) // (EFC) Sector 0 Lock Status
#define AT91C_MC_GPNVM1 (0x1 << 9) // (EFC) Sector 1 Lock Status
#define AT91C_MC_GPNVM2 (0x1 << 10) // (EFC) Sector 2 Lock Status
#define AT91C_MC_GPNVM3 (0x1 << 11) // (EFC) Sector 3 Lock Status
#define AT91C_MC_GPNVM4 (0x1 << 12) // (EFC) Sector 4 Lock Status
#define AT91C_MC_GPNVM5 (0x1 << 13) // (EFC) Sector 5 Lock Status
#define AT91C_MC_GPNVM6 (0x1 << 14) // (EFC) Sector 6 Lock Status
#define AT91C_MC_GPNVM7 (0x1 << 15) // (EFC) Sector 7 Lock Status
#define AT91C_MC_LOCKS0 (0x1 << 16) // (EFC) Sector 0 Lock Status
#define AT91C_MC_LOCKS1 (0x1 << 17) // (EFC) Sector 1 Lock Status
#define AT91C_MC_LOCKS2 (0x1 << 18) // (EFC) Sector 2 Lock Status
#define AT91C_MC_LOCKS3 (0x1 << 19) // (EFC) Sector 3 Lock Status
#define AT91C_MC_LOCKS4 (0x1 << 20) // (EFC) Sector 4 Lock Status
#define AT91C_MC_LOCKS5 (0x1 << 21) // (EFC) Sector 5 Lock Status
#define AT91C_MC_LOCKS6 (0x1 << 22) // (EFC) Sector 6 Lock Status
#define AT91C_MC_LOCKS7 (0x1 << 23) // (EFC) Sector 7 Lock Status
#define AT91C_MC_LOCKS8 (0x1 << 24) // (EFC) Sector 8 Lock Status
#define AT91C_MC_LOCKS9 (0x1 << 25) // (EFC) Sector 9 Lock Status
#define AT91C_MC_LOCKS10 (0x1 << 26) // (EFC) Sector 10 Lock Status
#define AT91C_MC_LOCKS11 (0x1 << 27) // (EFC) Sector 11 Lock Status
#define AT91C_MC_LOCKS12 (0x1 << 28) // (EFC) Sector 12 Lock Status
#define AT91C_MC_LOCKS13 (0x1 << 29) // (EFC) Sector 13 Lock Status
#define AT91C_MC_LOCKS14 (0x1 << 30) // (EFC) Sector 14 Lock Status
#define AT91C_MC_LOCKS15 (0x1 << 31) // (EFC) Sector 15 Lock Status
// -------- EFC_VR : (EFC Offset: 0xc) EFC version register --------
#define AT91C_EFC_VERSION (0xFFF << 0) // (EFC) EFC version number
#define AT91C_EFC_MFN (0x7 << 16) // (EFC) EFC MFN
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Serial Parallel Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SPI {
AT91_REG SPI_CR; // Control Register
AT91_REG SPI_MR; // Mode Register
AT91_REG SPI_RDR; // Receive Data Register
AT91_REG SPI_TDR; // Transmit Data Register
AT91_REG SPI_SR; // Status Register
AT91_REG SPI_IER; // Interrupt Enable Register
AT91_REG SPI_IDR; // Interrupt Disable Register
AT91_REG SPI_IMR; // Interrupt Mask Register
AT91_REG Reserved0[4]; //
AT91_REG SPI_CSR[4]; // Chip Select Register
AT91_REG Reserved1[48]; //
AT91_REG SPI_RPR; // Receive Pointer Register
AT91_REG SPI_RCR; // Receive Counter Register
AT91_REG SPI_TPR; // Transmit Pointer Register
AT91_REG SPI_TCR; // Transmit Counter Register
AT91_REG SPI_RNPR; // Receive Next Pointer Register
AT91_REG SPI_RNCR; // Receive Next Counter Register
AT91_REG SPI_TNPR; // Transmit Next Pointer Register
AT91_REG SPI_TNCR; // Transmit Next Counter Register
AT91_REG SPI_PTCR; // PDC Transfer Control Register
AT91_REG SPI_PTSR; // PDC Transfer Status Register
} AT91S_SPI, *AT91PS_SPI;
#else
#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register
#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register
#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register
#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register
#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register
#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register
#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register
#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register
#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register
#endif
// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable
#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable
#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset
#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer
// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode
#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select
#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select
#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select
#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode
#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection
#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection
#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection
#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select
#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects
// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data
#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data
#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full
#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty
#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error
#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status
#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer
#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer
#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt
#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt
#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt
#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt
#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status
// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity
#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase
#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer
#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK
#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Usart
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_USART {
AT91_REG US_CR; // Control Register
AT91_REG US_MR; // Mode Register
AT91_REG US_IER; // Interrupt Enable Register
AT91_REG US_IDR; // Interrupt Disable Register
AT91_REG US_IMR; // Interrupt Mask Register
AT91_REG US_CSR; // Channel Status Register
AT91_REG US_RHR; // Receiver Holding Register
AT91_REG US_THR; // Transmitter Holding Register
AT91_REG US_BRGR; // Baud Rate Generator Register
AT91_REG US_RTOR; // Receiver Time-out Register
AT91_REG US_TTGR; // Transmitter Time-guard Register
AT91_REG Reserved0[5]; //
AT91_REG US_FIDI; // FI_DI_Ratio Register
AT91_REG US_NER; // Nb Errors Register
AT91_REG Reserved1[1]; //
AT91_REG US_IF; // IRDA_FILTER Register
AT91_REG Reserved2[44]; //
AT91_REG US_RPR; // Receive Pointer Register
AT91_REG US_RCR; // Receive Counter Register
AT91_REG US_TPR; // Transmit Pointer Register
AT91_REG US_TCR; // Transmit Counter Register
AT91_REG US_RNPR; // Receive Next Pointer Register
AT91_REG US_RNCR; // Receive Next Counter Register
AT91_REG US_TNPR; // Transmit Next Pointer Register
AT91_REG US_TNCR; // Transmit Next Counter Register
AT91_REG US_PTCR; // PDC Transfer Control Register
AT91_REG US_PTSR; // PDC Transfer Status Register
} AT91S_USART, *AT91PS_USART;
#else
#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register
#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register
#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register
#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register
#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (⌨️ 快捷键说明
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