displayport.c

realtek LCD monitor, TV开发源代码

        pData[1]=16;

    OffsetLine = 1536*(WORD)(ucDisplayPortCtrl&0x07)/(WORD)pData[1];

    FrontPorchValueData = (((DWORD)(HtotalValueData-HwidthValueData-HstartValueData+OffsetLine)) * NvidValueData/MvidValueData);
//end of eagleeyes-20080309

     pData[0]=(FrontPorchValueData>>24);
     if(pData[0]==0)
        return(FrontPorchValueData);
     else
        return(0x000002);
}
#endif //End of #if(_FRONT_PORCH_REGENERATOR == _ON)

//--------------------------------------------------
// Description  : Display Format Initial of Display Port
// Input Value  : None
// Output Value : None
//--------------------------------------------------
void CDpDisplayFormatInitial(void)
{
#if(_FRONT_PORCH_REGENERATOR == _ON)
    DWORD VsyncFrontPorchValue,HsyncFrontPorchValue,FrontPorchValue;
#endif // End of #if(_Front_Porch_Regenerator == _ON)
    CScalerPageSelect(_PAGEC);
#if(_DP_DISPLAY_FORMAT_SEL == _FRAME_SYNC_MODE)       //start format @ frame-sync mode
     //bit7=start bit. 1-->start to generate
    //bit6=double buffer. 1-->double buffer active
    //bit5=HS/VS generation. 1-->framep-sync, 0-->full last line
    //bit4=DE generation. 1-->digital mode, 0: normal mode
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x35, 0xA0);
#endif // End of #if(_DP_DISPLAY_FORMAT_SEL == _FRAME_SYNC_MODE)

#if(_DP_DISPLAY_FORMAT_SEL == _FULL_LAST_LINE)     //start format @ full-last mode
    //bit7=start bit. 1-->start to generate
    //bit6=double buffer. 1-->double buffer active
    //bit5=HS/VS generation. 1-->framep-sync, 0-->full last line
    //bit4=DE generation. 1-->digital mode, 0: normal mode                                                                       //bit4=DE generation. 1-->digital mode, 0: normal mode
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x35, 0x80);
#endif // End of #if(_DP_DISPLAY_FORMAT_SEL == _FULL_LAST_LINE)
    //The delay count of link clk for "BS or BE to Virtual VS" in even field
    pData[0]=0x00; //H
    pData[1]=0x00; //M //640pixels*2lines*24bits div 10 = 0xC00
    pData[2]=0x02; //L
#if(_FRONT_PORCH_REGENERATOR == _ON)
    VsyncFrontPorchValue = CDpGetVsyncFrontPorch();
    HsyncFrontPorchValue=CDpGetHsyncFrontPorch();
    FrontPorchValue = ( VsyncFrontPorchValue + HsyncFrontPorchValue )*100/100;// + 0x100;
    pData[0]=(FrontPorchValue>>16);
    pData[1]=(FrontPorchValue>>8);
    pData[2]=(FrontPorchValue>>0);
    CScalerWrite(0xC5, 3, pData, _AUTOINC);   //LSB delay value
#endif // End of #if(_Front_Porch_Regenerator == _ON)
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x36, pData[0]);
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x37, pData[1]);
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x38, pData[2]);
   //The delay count of link clk for "BS or BE to Virtual VS" in odd field
    pData[0]=0x00; //H
    pData[1]=0x00; //M //640pixels*2lines*24bits div 10 = 0xC00
    pData[2]=0x02; //L
#if(_FRONT_PORCH_REGENERATOR == _ON)
    VsyncFrontPorchValue = CDpGetVsyncFrontPorch();
    HsyncFrontPorchValue = CDpGetHsyncFrontPorch();
    FrontPorchValue = (VsyncFrontPorchValue + HsyncFrontPorchValue)*100/100;
    pData[0]=(FrontPorchValue>>16);
    pData[1]=(FrontPorchValue>>8);
    pData[2]=(FrontPorchValue>>0);
#endif // End of #if(_Front_Porch_Regenerator == _ON)
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x39, pData[0]);
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x3A, pData[1]);
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x3B, pData[2]);
  //The delay count of link clk for "BS or BE to DE" in digital mode
    pData[1]=0x00;
    pData[0]=0x00;
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x3C, pData[1]);
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x3D, pData[0]);
  //Set Htotal
    CScalerGetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x04, 2, pData, _NON_AUTOINC);
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x3E, pData[0]);
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x3F, pData[1]);
  //Set Hstart
    CScalerGetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x06, 2, pData, _NON_AUTOINC);
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x40, pData[0]);
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x41, pData[1]);
  //Set Hwidth
    CScalerGetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x08, 2, pData, _NON_AUTOINC);
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x42, pData[0]);
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x43, pData[1]);
  //Set HSW
    CScalerGetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x0A, 2, pData, _NON_AUTOINC);
    pData[0] &= 0x7F; //set pority in plus
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x44, pData[0]);
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x45, pData[1]);
    CScalerGetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x01, 1, pData, _NON_AUTOINC);
    if ((pData[0]&0x06)==0x06)  //Set ODD-Vtotal if interlace-ODD
        CScalerGetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x0E, 2, pData, _NON_AUTOINC);
    else  //Set Even-Vtotal if interlace-EVEN or progressive
        CScalerGetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x0C, 2, pData, _NON_AUTOINC);
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x46, pData[0]);
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x47, pData[1]);
  //Set Vstart
    CScalerGetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x10, 2, pData, _NON_AUTOINC);
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x48, pData[0]);
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x49, pData[1]);
  //Set Vheight
    CScalerGetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x12, 2, pData, _NON_AUTOINC);
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x4A, pData[0]);
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x4B, pData[1]);
  //Set VSP and VSW
    CScalerGetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x14, 2, pData, _NON_AUTOINC);
    pData[0] &= 0x7F;    //set pority in plus
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x4C, pData[0]);
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x4D, pData[1]);
#if(_DP_DISPLAY_FORMAT_SEL == _FRAME_SYNC_MODE)
    //bit7=start bit. 1-->start to generate
    //bit6=double buffer. 1-->double buffer active
    //bit5=HS/VS generation. 1-->framep-sync, 0-->full last line
    //bit4=DE generation. 1-->digital mode, 0: normal mode
     CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x35, 0xE0);
#endif // End of #if(_DP_DISPLAY_FORMAT_SEL == _FRAME_SYNC_MODE)
#if(_DP_DISPLAY_FORMAT_SEL == _FULL_LAST_LINE)
    //bit7=start bit. 1-->start to generate
    //bit6=double buffer. 1-->double buffer active
    //bit5=HS/VS generation. 1-->framep-sync, 0-->full last line
    //bit4=DE generation. 1-->digital mode, 0: normal mode
     CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x35, 0xC0);
#endif // End of #if(_DP_DISPLAY_FORMAT_SEL == _FULL_LAST_LINE)
}
//--------------------------------------------------
// Description  : Display port vedio fifo Auto-Test Function
// Input Value  : None
// Output Value : True: BIST PASS, False: BIST Fail
//--------------------------------------------------
bit CDpIsFifoMemoryPass(void)
{
    CScalerPageSelect(_PAGEC);
    CScalerSetByte(_PC_DP_MEM_BIST_B2, 0x05);
    CScalerRead(_PC_DP_MEM_BIST_B2, 1, pData, _NON_AUTOINC);
    while((( pData[0]&0x04)==0x04)||((pData[0]&0x01)==0x01))
    {
       CScalerRead(_PC_DP_MEM_BIST_B2, 1, pData, _NON_AUTOINC);
    }
    if (pData[0]==0x0A)
        return _TRUE;
    else
        return _FALSE;
}

//--------------------------------------------------
// Description  : Display port vedio fifo Auto-Test Function
// Input Value  : None
// Output Value : True: BIST PASS, False: BIST Fail
//--------------------------------------------------
bit CDpIsFifoUnderOverFlow(void)
{
    CScalerPageSelect(_PAGEC);
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x30, 0xff);
    CTimerDelayXms(30); // 30:MN_Tracking , 70:VS_Tracking
    CScalerGetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x30, 1, pData, _NON_AUTOINC);
//eagleeyes-20080313
    if( (pData[0]&0x80)==0x80)
        return _TRUE;

    else if( (pData[0]&0x40)==0x40)
        return _TRUE;

    else
        return _FALSE;
/*
    if( (pData[0]&0x08)==0x08)    // whhsiao + VerB
        return _TRUE;          //video fifo overflow
    else if( (pData[0]&0x01)==0x01) // whhsiao VerA/B the same
        return _TRUE;          //small fifo underflow
    else if( (pData[0]&0x12)==0x12)   // whhsiao + VerB
        return _FALSE;          //small fifo non-empty
    else
        return _TRUE;
*/
}
//--------------------------------------------------
// Description  : DP MAC INITIALTION
// Input Value  : None
// Output Value : None
//--------------------------------------------------
void CDpMacInitial(void)
{
    BYTE buf=0;
    CScalerPageSelect(_PAGEC);
    if(GET_DP_ENHANCEMENT_MODE())
    {
        buf|=0x04;
    }
    CScalerPageSelect(_PAGEB);
    CScalerSetByte(_PB_DIG00_E0,0xC0);
    CScalerPageSelect(_PAGEC);
    if(GET_DP_ONE_LANE_INPUT())
    {
        buf|=0x08;
        CScalerSetByte(_PC_DP_CTL_A1, buf);
        CScalerSetByte(_PC_DP_OUTPUT_CTL_A2, 0xF0);
        CScalerSetByte(_PC_MIN_DE_SKEW_A8, 0x00); //0x0: disable all de-skew circuit
        CScalerSetByte(_PC_MN_ERRC_A9, 0x00); //0x0:disable error correction, 0xF4:enable all error correction
    }
    if(GET_DP_TWO_LANE_INPUT())
    {
    buf|=0x10;
        CScalerSetByte(_PC_DP_CTL_A1, buf);
        CScalerSetByte(_PC_DP_OUTPUT_CTL_A2, 0xF0);
        CScalerSetByte(_PC_MIN_DE_SKEW_A8, 0x1C); //0x0: disable all de-skew circuit
        CScalerSetByte(_PC_MN_ERRC_A9, 0x00); //0x0:disable error correction, 0xF4:enable all error correction
    }
    if(GET_DP_FOUR_LANE_INPUT())
    {
    buf|=0x18;
        CScalerSetByte(_PC_DP_CTL_A1, buf);
        CScalerSetByte(_PC_DP_OUTPUT_CTL_A2, 0xF0);
        CScalerSetByte(_PC_MIN_DE_SKEW_A8, 0x1C); //0x0: disable all de-skew circuit
        CScalerSetByte(_PC_MN_ERRC_A9, 0x00); //0x0:disable error correction, 0xF4:enable all error correction
    }
    CScalerSetByte(0xA3,0x00);
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x00, 0xF8);  //pop up parameter
}

//--------------------------------------------------
// Description  : Display port FIFO Adjustment
// Input Value  : None
// Output Value : None
//--------------------------------------------------
//
void CDpAdjustVsyncDelayCount(void)
{
    BYTE buf;
    DWORD MaxBStoVSDelayValue,MinBStoVSDelayValue,CurrentBStoVSDelayValue;
    BYTE FifoErrorCnt=0;
    bit forwardtrace;
    CScalerPageSelect(_PAGEC);
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x5E, 0x2A);
    CTimerDelayXms(30);
    CScalerGetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x5E, 1, pData, _NON_AUTOINC);
    buf=0;
    while((pData[0]&0x20)==0x20)
    {
       CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x5E, 0x2A);
       CTimerDelayXms(30);
       CScalerGetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x5E, 1, pData, _NON_AUTOINC);
//eagleeyes-20080215
//bLED9=~bLED9;
       CMiscIspDebugProc(); //Anderson 080512
       if(buf<=15)
          buf++;
       else
          break;
    }
    CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x30, 0xFF);
    CTimerDelayXms(50);
    CScalerGetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x30, 1, pData, _NON_AUTOINC);
    if ((pData[0]&0x80)==0x80) //earily overflow  --> backward trace
        forwardtrace=0;
    else
        forwardtrace=1; //earily underflow and non-overflow/non-underflow
    CScalerPageSelect(_PAGEC);
    CScalerGetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x36, 3, pData, _NON_AUTOINC);
    CurrentBStoVSDelayValue = ( ((DWORD)pData[0]<<16) | ((DWORD)pData[1]<<8) | ((DWORD)pData[2]<<0) );
    buf=0;
    if(CDpIsFifoUnderOverFlow()==_TRUE) //FIFO overflow/underflow
    {
       while((FifoErrorCnt<=_BOUNDARY_CHECK_NUM) && (buf<=_TIMEOUT_NUM) ) //eagleeeys 070926
       {
//eagleeyes-20080215
          CMiscIspDebugProc(); //Anderson 080512
          if( forwardtrace==1 ) //backward trace
             CurrentBStoVSDelayValue+=0x18;
          else
             CurrentBStoVSDelayValue-=0x18;
          pData[0]=(CurrentBStoVSDelayValue>>16);
          pData[1]=(CurrentBStoVSDelayValue>>8);
          pData[2]=(CurrentBStoVSDelayValue>>0);
          CScalerWrite(0xBA, 3, pData, _AUTOINC);   //LSB delay value
      //The delay count of link clk for "BS or BE to Virtual VS" in even field
          CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x36, pData[0]);
          CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x37, pData[1]);
          CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x38, pData[2]);
      //The delay count of link clk for "BS or BE to Virtual VS" in odd field
          CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x39, pData[0]);
          CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x3A, pData[1]);
          CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x3B, pData[2]);
#if(_DP_DISPLAY_FORMAT_SEL == _FRAME_SYNC_MODE)
          CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x35, 0x00);
          CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x35, 0xE0);
#endif // End of #if(_DP_DISPLAY_FORMAT_SEL == _FRAME_SYNC_MODE)
#if(_DP_DISPLAY_FORMAT_SEL == _FULL_LAST_LINE)
          CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x35, 0x00);
          CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x35, 0xC0);
#endif // End of #if(_DP_DISPLAY_FORMAT_SEL == _FULL_LAST_LINE)
          CTimerDelayXms(20); // 20:MN_Tracking , 60:VS_Tracking
          if(CDpIsFifoUnderOverFlow()==_FALSE) //eagleeeys 070926
          {
             FifoErrorCnt++; //OK
          }
          else //debug-eagle
          {// harry 20071212
             FifoErrorCnt = 0;
             buf++;  //Fail
          }
       }
    }
    MinBStoVSDelayValue=CurrentBStoVSDelayValue;
    ucDisplayPortStatus |= 0x20;        //FIND The Minmum BS to VS delay value, it make fifo not overflow and under flow
    CScalerSetByte (0xC9, ucDisplayPortStatus);
    if(CDpIsFifoUnderOverFlow()==_FALSE)
    {
        FifoErrorCnt = 0;
        while (FifoErrorCnt!=_SEARCH_RANGE)
        {
//eagleeyes-20080401
#if ((_PCB_TYPE == _RTD2472D_QA_PCB) || (_SCALER_TYPE == _RTD247xRD))
            bLED2=~bLED2;
#endif
           CMiscIspDebugProc(); //Anderson 080512
           if(forwardtrace==1 ) //backward trace
              CurrentBStoVSDelayValue+=0x18;
           else
              CurrentBStoVSDelayValue-=0x18;
           pData[0]=(CurrentBStoVSDelayValue>>16);
           pData[1]=(CurrentBStoVSDelayValue>>8);
           pData[2]=(CurrentBStoVSDelayValue>>0);
           CScalerWrite(0xBD, 3, pData, _AUTOINC);   //MSB delay value
         //The delay count of link clk for "BS or BE to Virtual VS" in even field
           CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x36, pData[0]);
           CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x37, pData[1]);
           CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x38, pData[2]);
         //The delay count of link clk for "BS or BE to Virtual VS" in odd field
           CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x39, pData[0]);
           CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x3A, pData[1]);
           CScalerSetDataPortByte(_PC_DP_ACCESS_PORT_B3, 0x3B, pData[2]);
#if(_DP_DI