📄 displayport.c
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//**********************************************************************************************************
// The Software is proprietary, confidential, and valuable to Realtek Semiconductor
// Corporation ("Realtek"). All rights, including but not limited to copyrights,
// patents, trademarks, trade secrets, mask work rights, and other similar rights and interests,
// are reserved to Realtek. Without prior written consent from Realtek, copying, reproduction,
// modification, distribution, or otherwise is strictly prohibited. The Software shall be
// kept strictly in confidence, and shall not be disclosed to or otherwise accessed by
// any third party. @ <2003> - <2008> The Software is provided "AS IS" without any warranty of any kind,
// express, implied, statutory or otherwise.
//**********************************************************************************************************
//----------------------------------------------------------------------------------------------------
// ID Code : DisplayPort.c No.0000
// Update Note :
//----------------------------------------------------------------------------------------------------
#define __DISPLAYPORT__
#include "Common\Header\Include.h"
//Anderson 071219 for 2545LR, 248xRD, 248xRD
#if(_SCALER_SERIES_TYPE == _RTD2472D_SERIES)
#if(_DP_SUPPORT == _ON)
//--------------------------------------------------
// Description : AUX Link Training Pattern 1 interrupt
// Input Value :
// Output Value :
//--------------------------------------------------
//eagleeyes-20080305-interrupt
void CDpTrainPattern1(void)
{
BYTE xdata dpprate,dplane,TP1_Error,Link_clock;
BYTE xdata Training_Lane_Set;
BYTE xdata buf;
CScalerSetByteInt(_PAGE_SELECT_9F,_PAGEC);
CScalerSetByteInt(0xc1, 0x00);
CScalerSetByteInt(0xc2, 0x01);
CScalerSetByteInt(0xc3, 0x00);
CScalerReadByteInt(0xc4, &dpprate); //read
CScalerSetByteInt(0xc3, 0x01);
CScalerReadByteInt(0xc4, &dplane); //read source lane
CScalerSetByteInt(0xb3, 0xb3);
CScalerSetByteInt(0xb4, 0x00);
if((dpprate&0x0A)== 0x0A )//Read source link BW 2.7G
{
//Mode detect
CScalerSetByteInt(_PAGE_SELECT_9F,_PAGEB);
CScalerSetByteInt(0xB4,0x00); //disable CMU
CScalerSetByteInt(0xB1,0x32);//test chip only
CScalerSetByteInt(0xB2,0x06); //0x16 eagle071221
CScalerSetByteInt(0xE0,0xC0);
CScalerSetByteInt(0xAF,0x87);
CScalerSetByteInt(_PB_DP_ADP_EQ_B2,0x76); // whhsiao added. 20080414
//eagleeyes-20080513
CScalerSetByteInt(0xA3,0x8C); // disable CMU (PHY CTS)
CScalerSetByteInt(0xAE,0x01); // test chip only (PHY CTS)
//eagleeyes-20080513
CScalerSetByteInt(0xB4,0xff); // 0x11 for one lane, 0xff for four lane
for (buf=0;buf<=20;buf++) // Wait for Stable of Phy Power ON/OFF // Min_value = 0x04
_nop_(); // Setp : 6usec
CScalerSetByteInt(0xB0,0x8D);
CScalerSetByteInt(0xB0,0x0D);
//Set 2.7Ghz Bandwidth
CScalerSetByteInt(0xA1,0x32); // whhsiao VerA -
//CScalerSetByteInt(0xA2,0x20); //old para.
CScalerSetByteInt(0xA2,0x06); //new para.
//CScalerSetByteInt(0xA2,0x04); //test para.
CScalerSetByteInt(0xBF,0xf0); // whhsiao VerA/B the same (erasable for VerB)
CScalerSetByteInt(0xAD,0x07); //0x07 // whhsiao - VerA
CScalerSetByteInt(0xAF,0xc7);
CScalerSetByteInt(0xAE,0xa1);
CScalerSetByteInt(0xE1,0xf0); //add by eagle080103
}
if((dpprate&0x06)== 0x06 )//Read source link BW 1.62G
{
//Mode detect
CScalerSetByteInt(_PAGE_SELECT_9F,_PAGEB);
CScalerSetByteInt(0xB4,0x00); //disable CMU
CScalerSetByteInt(0xB1,0x32); //test chip only
CScalerSetByteInt(0xB2,0x06); //0x16 eagle071221
CScalerSetByteInt(0xE0,0xC0);
CScalerSetByteInt(0xAF,0x87);
CScalerSetByteInt(_PB_DP_ADP_EQ_B2,0x76); // whhsiao added. 20080414
//eagleeyes-20080513
CScalerSetByteInt(0xA3,0x8C); // disable CMU (PHY CTS)
CScalerSetByteInt(0xAE,0x01); // test chip only (PHY CTS)
//eagleeyes-20080513
CScalerSetByteInt(0xB4,0xff); //0x11 for one lane, 0xff for four lane
for (buf=0;buf<=20;buf++) // Wait for Stable of Phy Power ON/OFF // Min_value = 0x04
_nop_(); // Setp : 6usec
CScalerSetByteInt(0xB0,0x8D);
CScalerSetByteInt(0xB0,0x0D);
//Set 1.62G Bandwidth
CScalerSetByteInt(0xa1,0x72); //old para.
CScalerSetByteInt(0xa2,0x24); //old para.
//CScalerSetByteInt(0xa1,0x02); //new para.
//CScalerSetByteInt(0xa2,0x46); //new para.
CScalerSetByteInt(0xbf,0xf0);
CScalerSetByteInt(0xad,0x07); //old para.
//CScalerSetByteInt(0xad,0x27); //new para.
CScalerSetByteInt(0xaf,0xc7);
CScalerSetByteInt(0xBA,0xC0);
CScalerSetByteInt(0xE1,0xF0);
}
CScalerSetByteInt(0xe2, 0xC0); // scramble disable
if ( (dplane&0x01)== 0x01 ) //1 lane
{
CScalerSetByteInt(0xe0, 0xC0);
CScalerSetByteInt(0xb4, 0x11);
for (buf=0;buf<=10;buf++) // Wait for Stable of Phy Power ON/OFF
_nop_();
// Lane_0 D10.2 Check
if((dpprate&0x0A)== 0x0A)
{
CScalerSetByteInt(_PAGE_SELECT_9F,_PAGEC);
CScalerSetByteInt(0xA4, 0x00);
CScalerSetByteInt(_PAGE_SELECT_9F,_PAGE2);
CScalerSetByteInt(0xC9, 0x28);
CScalerSetByteInt(0xCA, 0x08);
CScalerSetByteInt(0xC9, 0x29);
CScalerReadByteInt(0xCA, &Link_clock);
if ( (Link_clock==0x66)||(Link_clock==0x67) )
TP1_Error = 0x00;
else
TP1_Error = 0x08;
}
else if ((dpprate&0x06)== 0x06)
{
CScalerSetByteInt(_PAGE_SELECT_9F,_PAGEC);
CScalerSetByteInt(0xA1,0x1C);
CScalerSetByteInt(0xA5,0xff);
CScalerReadByteInt(0xA5, &TP1_Error);
}
if ((TP1_Error&0x08)==0x00)
Lane01_Status |= 0x01;
else
{
Lane01_Status &= 0xFE;
CScalerSetByteInt(_PAGE_SELECT_9F,_PAGEC);
CScalerSetByteInt(0xc1, 0x00);
CScalerSetByteInt(0xc2, 0x01);
CScalerSetByteInt(0xc3, 0x03);
CScalerReadByteInt(0xc4, &Training_Lane_Set);
// Adjust_Request_L01 = (Adjust_Request_L01 & 0xFC) | (Training_Lane_Set & 0x03); // whhsiao-added.20080506
Adjust_Request_L01 = (Adjust_Request_L01 & 0xF0) | (Training_Lane_Set & 0x03) | ((Training_Lane_Set & 0x18)<<1); // whhsiao-added.20080506
if ( ((Training_Lane_Set&0x04)==0x00) && ((Adjust_Request_L01&0x03)!=0x03) )
Adjust_Request_L01 = Adjust_Request_L01 + 0x01;
}
if ((Lane01_Status&0x01)==0x01)
ucDisplayPortLtPreStatus = _TRAINING_PATTERN1_PASS;
}
else if ( (dplane&0x02)== 0x02 ) //2 lane
{
CScalerSetByteInt(0xe0, 0xC0);
if(dpprate==0x06)
CScalerSetByteInt(0xb4, 0x00); // povich
CScalerSetByteInt(0xb4, 0x33);
for (buf=0;buf<=10;buf++) // Wait for Stable of Phy Power ON/OFF
_nop_();
// Lane_0 D10.2 Check
if((dpprate&0x0A)== 0x0A)
{
CScalerSetByteInt(_PAGE_SELECT_9F,_PAGEC);
CScalerSetByteInt(0xA4, 0x00);
CScalerSetByteInt(_PAGE_SELECT_9F,_PAGE2);
CScalerSetByteInt(0xC9, 0x28);
CScalerSetByteInt(0xCA, 0x08);
CScalerSetByteInt(0xC9, 0x29);
CScalerReadByteInt(0xCA, &Link_clock);
if ( (Link_clock==0x66)||(Link_clock==0x67) )
TP1_Error = 0x00;
else
TP1_Error = 0x08;
}
else if ((dpprate&0x06)== 0x06)
{
CScalerSetByteInt(_PAGE_SELECT_9F,_PAGEC);
CScalerSetByteInt(0xA1,0x1C);
CScalerSetByteInt(0xA5,0xff);
CScalerReadByteInt(0xA5, &TP1_Error);
}
if ((TP1_Error&0x08)==0x00)
Lane01_Status |= 0x01;
else
{
Lane01_Status &= 0xFE;
CScalerSetByteInt(_PAGE_SELECT_9F,_PAGEC);
CScalerSetByteInt(0xc1, 0x00);
CScalerSetByteInt(0xc2, 0x01);
CScalerSetByteInt(0xc3, 0x03);
CScalerReadByteInt(0xc4, &Training_Lane_Set);
// Adjust_Request_L01 = (Adjust_Request_L01 & 0xFC) | (Training_Lane_Set & 0x03); // whhsiao-added.20080506
Adjust_Request_L01 = (Adjust_Request_L01 & 0xF0) | (Training_Lane_Set & 0x03) | ((Training_Lane_Set & 0x18)<<1); // whhsiao-added.20080506
if ( ((Training_Lane_Set&0x04)==0x00) && ((Adjust_Request_L01&0x03)!=0x03) )
Adjust_Request_L01 = Adjust_Request_L01 + 0x01;
}
// Lane_1 D10.2 Check
if((dpprate&0x0A)== 0x0A)
{
CScalerSetByteInt(_PAGE_SELECT_9F,_PAGEC);
CScalerSetByteInt(0xA4, 0x55);
CScalerSetByteInt(_PAGE_SELECT_9F,_PAGE2);
CScalerSetByteInt(0xC9, 0x28);
CScalerSetByteInt(0xCA, 0x08);
CScalerSetByteInt(0xC9, 0x29);
CScalerReadByteInt(0xCA, &Link_clock);
if ( (Link_clock==0x66)||(Link_clock==0x67) )
TP1_Error &= 0xFB;
else
TP1_Error |= 0x04;
}
if ((TP1_Error&0x04)==0x00)
Lane01_Status |= 0x10;
else
{
Lane01_Status &= 0xEF;
CScalerSetByteInt(_PAGE_SELECT_9F,_PAGEC);
CScalerSetByteInt(0xc1, 0x00);
CScalerSetByteInt(0xc2, 0x01);
CScalerSetByteInt(0xc3, 0x04);
CScalerReadByteInt(0xc4, &Training_Lane_Set);
// Adjust_Request_L01 = (Adjust_Request_L01 & 0xCF) | ((Training_Lane_Set & 0x03)<<4); // whhsiao-added.20080506
Adjust_Request_L01 = (Adjust_Request_L01 & 0x0F) | ((Training_Lane_Set & 0x03)<<4) | ((Training_Lane_Set & 0x18)<<3); // whhsiao-added.20080506
if ( ((Training_Lane_Set&0x04)==0x00) && ((Adjust_Request_L01&0x30)!=0x30) )
Adjust_Request_L01 = Adjust_Request_L01 + 0x10;
}
if ((Lane01_Status&0x11)==0x11)
ucDisplayPortLtPreStatus = _TRAINING_PATTERN1_PASS;
}
else //4 lane
{
CScalerSetByteInt(0xe0, 0xc0); //eagleeyes-20080214
if(dpprate==0x06)
CScalerSetByteInt(0xb4, 0x00); // povich
CScalerSetByteInt(0xb4, 0xff);
for (buf=0;buf<=10;buf++) // Wait for Stable of Phy Power ON/OFF
_nop_();
// Lane_0 D10.2 Check
if((dpprate&0x0A)== 0x0A)
{
CScalerSetByteInt(_PAGE_SELECT_9F,_PAGEC);
CScalerSetByteInt(0xA4, 0x00);
CScalerSetByteInt(_PAGE_SELECT_9F,_PAGE2);
CScalerSetByteInt(0xC9, 0x28);
CScalerSetByteInt(0xCA, 0x08);
CScalerSetByteInt(0xC9, 0x29);
CScalerReadByteInt(0xCA, &Link_clock);
if ( (Link_clock==0x66)||(Link_clock==0x67) )
TP1_Error = 0x00;
else
TP1_Error = 0x08;
}
else if ((dpprate&0x06)== 0x06)
{
CScalerSetByteInt(_PAGE_SELECT_9F,_PAGEC);
CScalerSetByteInt(0xA1,0x1C);
CScalerSetByteInt(0xA5,0xff);
CScalerReadByteInt(0xA5, &TP1_Error);
}
if ((TP1_Error&0x08)==0x00)
Lane01_Status |= 0x01;
else
{
Lane01_Status &= 0xFE;
CScalerSetByteInt(_PAGE_SELECT_9F,_PAGEC);
CScalerSetByteInt(0xc1, 0x00);
CScalerSetByteInt(0xc2, 0x01);
CScalerSetByteInt(0xc3, 0x03);
CScalerReadByteInt(0xc4, &Training_Lane_Set);
// Adjust_Request_L01 = (Adjust_Request_L01 & 0xFC) | (Training_Lane_Set & 0x03); // whhsiao-added.20080506
Adjust_Request_L01 = (Adjust_Request_L01 & 0xF0) | (Training_Lane_Set & 0x03) | ((Training_Lane_Set & 0x18)<<1); // whhsiao-added.20080506
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