📄 displayport.h
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//**********************************************************************************************************
// The Software is proprietary, confidential, and valuable to Realtek Semiconductor
// Corporation ("Realtek"). All rights, including but not limited to copyrights,
// patents, trademarks, trade secrets, mask work rights, and other similar rights and interests,
// are reserved to Realtek. Without prior written consent from Realtek, copying, reproduction,
// modification, distribution, or otherwise is strictly prohibited. The Software shall be
// kept strictly in confidence, and shall not be disclosed to or otherwise accessed by
// any third party. @ <2003> - <2008> The Software is provided "AS IS" without any warranty of any kind,
// express, implied, statutory or otherwise.
//**********************************************************************************************************
//----------------------------------------------------------------------------------------------------
// ID Code : DisplayPort.h No.0000
// Update Note :
//----------------------------------------------------------------------------------------------------
//--------------------------------------------------
// StreamClk Regenerator DPLLMode
// Recommand function: VS Tracking mode
//--------------------------------------------------
#define _XTAL 0
#define _LINKCLK 1
#define _DP_DPLL_INPUT_SEL _XTAL
//--------------------------------------------------
//Tracking Mode
// recommand function: VS Tracking mode
//--------------------------------------------------
#define _NONE_TRACKING 0
#define _MNTRACKING 1
#define _VSTRACKING 2
#define _VS_AND_MN_TRACKING 3
#define _TRACKING_MODE _MNTRACKING
//--------------------------------------------------
//Tracking FIFO overflow underflow Mode
//--------------------------------------------------
#define _FRONT_PORCH_REGENERATOR _ON
//--------------------------------------------------
// Display Format
// recommand function: full last line mode
//--------------------------------------------------
#define _FRAME_SYNC_MODE 0
#define _FULL_LAST_LINE 1
#define _DP_DISPLAY_FORMAT_SEL _FRAME_SYNC_MODE
//--------------------------------------------------
// Regenerator StreamClk Style
//--------------------------------------------------
#define _BY_MN_VALUE 0
#define _BY_MEASUREMENT 1
#define _DP_STREAM_CLOCK_SEL _BY_MN_VALUE
//--------------------------------------------------
// YCbCr mode transfer to RGB Mode table enable or disable
//--------------------------------------------------
#define _YPBPR_TABLE_SET_SCALER _OFF
//--------------------------------------------------
// FIFO TRACKING TIMES
//_BOUNDARY_CHECK_NUM: from overflow/underflow go into non-overflow/underflow check ok times
//_SEARCH_RANGE: from Minmum value to Maxmum non-overflow/underflow check times (step 0x18 link clk)
//_TIMEOUT_NUM: In this range, If can't search the Minimum value, program will drop out to search state
//_PHY_DETECT_MODE_SEARCH_TIMES: after aux channel handshaking, PHY need to re-detect D10.2 sync pattern to fine the speed bandwidth
//--------------------------------------------------
#define _BOUNDARY_CHECK_NUM 2 //7
#define _TIMEOUT_NUM 6
#define _SEARCH_RANGE 2
#define _HWIDTH_BUFFER_RATIO 2
#ifdef __DISPLAYPORT__
BYTE code tDP_NO_PORT_WARNING[] = { 0x00,}; //cyyeh 20080505
//--------------------------------------------------
// Global Variables
//--------------------------------------------------
BYTE xdata ucDisplayPortCtrl = 0;
BYTE xdata ucDisplayPortStatus = 0;
BYTE xdata ucDisplayPortLtPreStatus = 0;
//whhsiao-20080317-interrupt
BYTE xdata TP1_times = 0; // whhsiao-debug
BYTE xdata TP2_times = 0; // whhsiao-debug
BYTE xdata Lane01_Status = 0;
BYTE xdata Lane23_Status = 0;
BYTE xdata Adjust_Request_L01 = 0;
BYTE xdata Adjust_Request_L23 = 0;
//--------------------------------------------------
// Display port Table
//--------------------------------------------------
BYTE code tDISP_PORT_IRQCLEAR[] =
{
4, _NON_AUTOINC, _PAGE_SELECT_9F, _PAGEC,//SDRAM Setting
4, _NON_AUTOINC, _PC_DP_ACCESS_PORT_B3, 0xcc,
4, _NON_AUTOINC, _PC_DP_DATA_PORT_B4, 0x80,
4, _NON_AUTOINC, _PC_AUX_IRQ_STATUS_DC, 0xff,
_END
};
BYTE code tDP_DPCD_INITIAL[] =
{
4, _NON_AUTOINC, _PAGE_SELECT_9F, _PAGEC,
7, _AUTOINC, _PC_DPCD_ACCESS_PORT_H_C1, 0x00,0x02,0x02,0x00,
7, _AUTOINC, _PC_DPCD_ACCESS_PORT_H_C1, 0x00,0x02,0x03,0x00,
7, _AUTOINC, _PC_DPCD_ACCESS_PORT_H_C1, 0x00,0x02,0x04,0x80,
_END
};
BYTE code tDP_AUX_INITIAL[] =
{
4, _NON_AUTOINC, _PAGE_SELECT_9F, _PAGEB,
4, _NON_AUTOINC, _PB_DIG03_E3, 0x01, //Anderson 071220 for typing error
5, _AUTOINC, _PB_DP_AUX_01_B8, 0x63,0x05,
4, _NON_AUTOINC, _PB_DP_AUX_00_B3, 0x80,
4, _NON_AUTOINC, _PB_DIG02_E2, 0x00,
_END
};
//--------------------------------------------------
// Function Prototypes
//--------------------------------------------------
void CDpTrainPattern1(void);
void CDpTrainPattern2(void);
void CDpTrainPatternEnd(void);
void CDpInitial(void);
void CDpReset(void);
void CDpInterruptInitial(void);
void CDpHotPlugProc(BYTE ms);
void CDpGetDisplayPortControl(void);
bit CDpIsDisplayPortPhyStable(void);
void CDpDetectPhySpeed(void);
DWORD CDpGetVsyncFrontPorch(void);
DWORD CDpGetHsyncFrontPorch(void);
void CDpDisplayFormatInitial(void);
bit CDpIsFifoMemoryPass(void);
bit CDpIsFifoUnderOverFlow(void);
void CDpMacInitial(void);
void CDpAdjustVsyncDelayCount(void);
void CDpVideoSetting(void);
bit CDpStreamClkRegeneratByMN(void);
bit CDpStreamClkRegeneratByHVtotal(void);
bit CDpStartupSetting(void); //eagleeyes-20080401
void CDpMacInitial(void);
void CDpInitial(void);
bit CDpIsDisplayPortVideoStream(void); //eagleeyes-20080401
//-------------------------------------------------
// Macro of One Lane Flag
//--------------------------------------------------
#define GET_DP_ONE_LANE_INPUT() (bit)(ucDisplayPortCtrl & _BIT0)
#define SET_DP_ONE_LANE_INPUT() ucDisplayPortCtrl |= _BIT0
#define CLR_DP_ONE_LANE_INPUT() ucDisplayPortCtrl &= ~_BIT0
//--------------------------------------------------
// Macro of Two Lane Flag
//--------------------------------------------------
#define GET_DP_TWO_LANE_INPUT() (bit)(ucDisplayPortCtrl & _BIT1)
#define SET_DP_TWO_LANE_INPUT() ucDisplayPortCtrl |= _BIT1
#define CLR_DP_TWO_LANE_INPUT() ucDisplayPortCtrl &= ~_BIT1
//--------------------------------------------------
// Macro of Four Lane Flag
//--------------------------------------------------
#define GET_DP_FOUR_LANE_INPUT() (bit)(ucDisplayPortCtrl & _BIT2)
#define SET_DP_FOUR_LANE_INPUT() ucDisplayPortCtrl |= _BIT2
#define CLR_DP_FOUR_LANE_INPUT() ucDisplayPortCtrl &= ~_BIT2
//--------------------------------------------------
// Macro of Enhancement Mode
//--------------------------------------------------
#define GET_DP_ENHANCEMENT_MODE() (bit)(ucDisplayPortCtrl & _BIT3)
#define SET_DP_ENHANCEMENT_MODE() ucDisplayPortCtrl |= _BIT3
#define CLR_DP_ENHANCEMENT_MODE() ucDisplayPortCtrl &= ~_BIT3
//--------------------------------------------------
// Macro of Scrambling Mode
//--------------------------------------------------
#define GET_DP_SCRAMB_MODE() (bit)(ucDisplayPortCtrl & _BIT4)
#define SET_DP_SCRAMB_MODE() ucDisplayPortCtrl |= _BIT4
#define CLR_DP_SCRAMB_MODE() ucDisplayPortCtrl &= ~_BIT4
//--------------------------------------------------
// Macro of 0.5% Down Spreading
//--------------------------------------------------
#define GET_DP_DOWN_SPREADING() (bit)(ucDisplayPortCtrl & _BIT5)
#define SET_DP_DOWN_SPREADING() ucDisplayPortCtrl |= _BIT5
#define CLR_DP_DOWN_SPREADING() ucDisplayPortCtrl &= ~_BIT5
//--------------------------------------------------
// Macro of 33Khz Modulation
//--------------------------------------------------
#define GET_DP_33KHZ_MODULATION() (bit)(ucDisplayPortCtrl & _BIT6)
#define SET_DP_33KHZ_MODULATION() ucDisplayPortCtrl |= _BIT6
#define CLR_DP_33KHZ_MODULATION() ucDisplayPortCtrl &= ~_BIT6
//--------------------------------------------------
// Macro of 2.7G Data rate
//--------------------------------------------------
#define GET_DP_HIGH_SPEED_RATE() (bit)(ucDisplayPortCtrl & _BIT7)
#define SET_DP_HIGH_SPEED_RATE() ucDisplayPortCtrl |= _BIT7
#define CLR_DP_HIGH_SPEED_RATE() ucDisplayPortCtrl &= ~_BIT7
#else
//--------------------------------------------------
// Extern Global Variables
//--------------------------------------------------
extern BYTE code tDISP_PORT_IRQCLEAR[];
extern BYTE code tDP_DPCD_INITIAL[];
extern BYTE xdata ucDisplayPortCtrl;
extern BYTE xdata ucDisplayPortStatus;
extern BYTE xdata ucDisplayPortLtPreStatus;
//whhsiao-20080317-interrupt
extern BYTE xdata TP1_times; // whhsiao-debug
extern BYTE xdata TP2_times; // whhsiao-debug
extern BYTE xdata Lane01_Status;
extern BYTE xdata Lane23_Status;
extern BYTE code tDP_NO_PORT_WARNING[]; //cyyeh 20080505
//--------------------------------------------------
// Extern Function Prototypes
//--------------------------------------------------
extern void CDpTrainPattern1(void);
extern void CDpTrainPattern2(void);
extern void CDpTrainPatternEnd(void);
extern void CDpInitial(void);
extern void CDpGetDisplayPortControl(void);
extern void CDpReset(void);
extern void CDpInterruptInitial(void);
extern void CDpHotPlugProc(BYTE ms);
extern bit CDpIsDisplayPortPhyStable(void);
//extern void CDpDetectPhySpeed(void);
extern DWORD CDpGetVsyncFrontPorch(void);
extern DWORD CDpGetHsyncFrontPorch(void);
extern void CDpDisplayFormatInitial(void);
extern bit CDpIsFifoMemoryPass(void);
extern bit CDpIsFifoUnderOverFlow(void);
extern void CDpMacInitial(void);
extern void CDpAdjustVsyncDelayCount(void);
extern void CDpVideoSetting(void);
extern bit CDpStreamClkRegeneratByMN(void);
extern bit CDpStreamClkRegeneratByHVtotal(void);
extern bit CDpStartupSetting(void); //eagleeyes-20080401
extern void CDpMacInitial(void);
extern bit CDpIsDisplayPortVideoStream(void); //eagleeyes-20080401
#endif // End of #ifdef __DISPLAYPORT__
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