scalerdef.h

realtek LCD monitor, TV开发源代码

#define _P5_SDRF_IN1_MEM_ADDR_L_AF          0xAF        // The Initial Write Address Of SDR Memory LByte
#define _P5_SDRF_IN1_LINE_STEP_H_B0         0xB0        // The Distance Between Two Lines Of SDR Memory HByte
#define _P5_SDRF_IN1_LINE_STEP_L_B1         0xB1        // The Distance Between Two Lines Of SDR Memory LByte
#define _P5_SDRF_IN1_BLOCK_STEP_H_B2        0xB2        // The Distance Between Two Blocks Of SDR Memory HByte
#define _P5_SDRF_IN1_BLOCK_STEP_L_B3        0xB3        // The Distance Between Two Blocks Of SDR Memory LByte
#define _P5_SDRF_IN1_BL2_ADDR_H_B4          0xB4        // Second Block Of SDR To Progress The Double Buffer. The Given Address Is The Absolute One HByte
#define _P5_SDRF_IN1_BL2_ADDR_M_B5          0xB5        // Second Block Of SDR To Progress The Double Buffer. The Given Address Is The Absolute One MByte
#define _P5_SDRF_IN1_BL2_ADDR_L_B6          0xB6        // Second Block Of SDR To Progress The Double Buffer. The Given Address Is The Absolute One LByte
#define _P5_SDRF_IN1_LINE_NUM_H_B7          0xB7        // The Total Line Number Of One Image HByte (Total 12 bits)
#define _P5_SDRF_IN1_LINE_NUM_L_B8          0xB8        // The Total Line Number Of One Image LByte (Total 12 bits)
#define _P5_SDRF_IN1_SDR_CTRL_B9            0xB9        // SDRAM IN1 FIFO Control Register
//Address: P5-BA Reserved
#define _P5_SDRF_IN1_SDR_STATUS_BB          0xBB        // SDRAM IN1 Status Register
#define _P5_SDRF_MN_PRERD_VST_H_BC          0xBC        // Vertical Start Line Of MAIN To Pre-Read Input Data HByte (Total 11-bits)
#define _P5_SDRF_MN_PRERD_VST_L_BD          0xBD        // Vertical Start Line Of MAIN To Pre-Read Input Data LByte (Total 11-bits)
#define _P5_SDRF_MN_PXL_NUM_H_BE            0xBE        // Pixel Number Of One Line, For FIFO To Clear Garbage From Capture Side HByte (Total 11-bits)
#define _P5_SDRF_MN_PXL_NUM_L_BF            0xBF        // Pixel Number Of One Line, For FIFO To Clear Garbage From Capture Side LByte (Total 11-bits)
#define _P5_SDRF_MN_WTLVL_C0                0xC0        // When FIFO Depth Is Under Water Level, FIFO Requests Data
//Address: P5-C1 Reserved
#define _P5_SDRF_MN_READ_NUM_H_C2           0xC2        // Number Of Length To Read From SDR In One Line HByte
#define _P5_SDRF_MN_READ_NUM_L_C3           0xC3        // Number Of Length To Read From SDR In One Line LByte
#define _P5_SDRF_MN_READ_LEN_C4             0xC4        // The Length Of Data To Read From SDR Once
#define _P5_SDRF_MN_READ_REMAIN_C5          0xC5        // The Remain Part That Can't Be A Complete Length In One Line
#define _P5_SDRF_MN_READ_ADDR_H_C6          0xC6        // The Initial Read Address Of SDR HByte (Total 23-bits)
#define _P5_SDRF_MN_READ_ADDR_M_C7          0xC7        // The Initial Read Address Of SDR MByte (Total 23-bits)
#define _P5_SDRF_MN_READ_ADDR_L_C8          0xC8        // The Initial Read Address Of SDR LByte (Total 23-bits)
#define _P5_SDRF_MN_LINE_STEP_H_C9          0xC9        // Line Step Indicates The Distance Between Two Lines HByte (Total 12 bits)
#define _P5_SDRF_MN_LINE_STEP_L_CA          0xCA        // Line Step Indicates The Distance Between Two Lines LByte (Total 12 bits)
#define _P5_SDRF_MN_BLOCK_STEP_H_CB         0xCB        // The Distance Between Two Blocks Of SDR HByte (Total 12-bits)
#define _P5_SDRF_MN_BLOCK_STEP_L_CC         0xCC        // The Distance Between Two Blocks Of SDR LByte (Total 12-bits)
#define _P5_SDRF_MN_LINE_NUM_H_CD           0xCD        // The Total Line Number Of One Image HByte (Total 12 bits)
#define _P5_SDRF_MN_LINE_NUM_L_CE           0xCE        // The Total Line Number Of One Image LByte (Total 12 bits)
#define _P5_SDRF_MN_DISP_CTRL_CF            0xCF        // SDRAM FIFO MAIN Display Control Register
#define _P5_SDRF_MN_SDR_STATUS_D0           0xD0        // SDRAM Status Register
//Address: P5-D1~P5-D5 Reserved
#define _P5_SDRF_ADC_TEST_D6                0xD6        // For ADC Test Usage
//Address: P5-D7~P5-E2 Reserved
#define _P5_SDRF_MN_FIFO_422_SET_E3         0xE3        // Output 444 Format(Only Work in FIFO 422 In Mode)
//Address: P5-E4~P5-FF Reserved


/////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////   Page 6: Reserved   ////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////

#elif(_SCALER_TYPE == _RTD2472D)
/////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////   Page 3: Reserved   ////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////
//Reserved Page (Page 3)


/////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////   Page 4: Reserved   ////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////
//Reserved Page (Page 4)


/////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////   Page 5: Reserved   ////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////
//Reserved Page (Page 5)


/////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////Page 6: Auto SOY///////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////

//--------------------------------------------------
// Auto SOY (Page6)
//--------------------------------------------------
#define _P6_SOY_CH0_CFG0_C0                 0xC0        // Auto Soy Channel 0 Control Register 0
#define _P6_SOY_CH0_CFG1_C1                 0xC1        // Auto Soy Channel 0 Control Register 1
#define _P6_SOY_CH0_CFG2_C2                 0xC2        // Auto Soy Channel 0 Control Register 2
#define _P6_SOY_CH0_CFG3_C3                 0xC3        // Auto Soy Channel 0 Control Register 3
#define _P6_SOY_CH0_CFG4_C4                 0xC4        // Auto Soy Channel 0 Control Register 4
#define _P6_SOY_CH0_CFG5_C5                 0xC5        // Auto Soy Channel 0 Control Register 5
#define _P6_SOY_CH0_CFG6_C6                 0xC6        // Auto Soy Channel 0 Control Register 6
#define _P6_SOY_CH0_CFG7_C7                 0xC7        // Auto Soy Channel 0 Control Register 7
#define _P6_SOY_CH0_CFG8_C8                 0xC8        // Auto Soy Channel 0 Control Register 8
#define _P6_SOY_CH0_CFG9_C9                 0xC9        // Auto Soy Channel 0 Control Register 9
#define _P6_SOY_CH0_CFGA_CA                 0xCA        // Auto Soy Channel 0 Control Register A
#define _P6_SOY_CH0_CFGB_CB                 0xCB        // Auto Soy Channel 0 Control Register B
#define _P6_SOY_CH0_CFGC_CC                 0xCC        // Auto Soy Channel 0 Control Register C
//#define _P6_RESERVED_CD                     0xCD        // PB Reserved CD
//#define _P6_RESERVED_CE                     0xCE        // PB Reserved CE
//#define _P6_RESERVED_CF                     0xCF        // PB Reserved CF

#define _P6_SOY_CH1_CFG0_D0                 0xD0        // Auto Soy Channel 1 Control Register 0
#define _P6_SOY_CH1_CFG1_D1                 0xD1        // Auto Soy Channel 1 Control Register 1
#define _P6_SOY_CH1_CFG2_D2                 0xD2        // Auto Soy Channel 1 Control Register 2
#define _P6_SOY_CH1_CFG3_D3                 0xD3        // Auto Soy Channel 1 Control Register 3
#define _P6_SOY_CH1_CFG4_D4                 0xD4        // Auto Soy Channel 1 Control Register 4
#define _P6_SOY_CH1_CFG5_D5                 0xD5        // Auto Soy Channel 1 Control Register 5
#define _P6_SOY_CH1_CFG6_D6                 0xD6        // Auto Soy Channel 1 Control Register 6
#define _P6_SOY_CH1_CFG7_D7                 0xD7        // Auto Soy Channel 1 Control Register 7
#define _P6_SOY_CH1_CFG8_D8                 0xD8        // Auto Soy Channel 1 Control Register 8
#define _P6_SOY_CH1_CFG9_D9                 0xD9        // Auto Soy Channel 1 Control Register 9
#define _P6_SOY_CH1_CFGA_DA                 0xDA        // Auto Soy Channel 1 Control Register A
#define _P6_SOY_CH1_CFGB_DB                 0xDB        // Auto Soy Channel 1 Control Register B
#define _P6_SOY_CH1_CFGC_DC                 0xDC        // Auto Soy Channel 1 Control Register C
//#define _P6_RESERVED_CD                     0xDD        // PB Reserved DD
//#define _P6_RESERVED_CE                     0xDE        // PB Reserved DE
//#define _P6_RESERVED_CF                     0xDF        // PB Reserved DF

#define _P6_SOY_CH0_CALI_CFG0_E0            0xE0        // Auto Soy Channel 0 Calibration Control Register 0
#define _P6_SOY_CH0_CALI_CFG1_E1            0xE1        // Auto Soy Channel 0 Calibration Control Register 0
#define _P6_SOY_CH0_CALI_CFG2_E2            0xE2        // Auto Soy Channel 0 Calibration Control Register 0
//#define _P6_RESERVED_E3                     0xE3        // PB Reserved E3
#define _P6_SOY_CH0_CALI_ADDR_PORT_E4       0xE4        // Auto Soy Channel 0 Calibration Address Port
#define _P6_SOY_CH0_CALI_DATA_PORT_E5       0xE5        // Auto Soy Channel 0 Calibration Data Port
//Address: P6-E6 ~ P6-EF Reserved

#define _P6_SOY_CH1_CALI_CFG0_F0            0xF0        // Auto Soy Channel 1 Calibration Control Register 0
#define _P6_SOY_CH1_CALI_CFG1_F1            0xF1        // Auto Soy Channel 1 Calibration Control Register 0
#define _P6_SOY_CH1_CALI_CFG2_F2            0xF2        // Auto Soy Channel 1 Calibration Control Register 0
//#define _P6_RESERVED_F3                     0xF3        // PB Reserved F3
#define _P6_SOY_CH1_CALI_ADDR_PORT_F4       0xF4        // Auto Soy Channel 1 Calibration Address Port
#define _P6_SOY_CH1_CALI_DATA_PORT_F5       0xF5        // Auto Soy Channel 1 Calibration Data Port
//Address: P6-F6 ~ P6-FF Reserved
#endif // End of #if((_SCALER_TYPE == _RTD2545LR) || (_SCALER_TYPE == _RTD247xRD) || (_SCALER_TYPE == _RTD248xRD))
//Anderson 071220 for 2545LR,247xRD,248xRD End


/////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////Page 7: Vivid Color////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////

//Address: P7-A0 ~ P7-BE Reserved

//Anderson 071220 for 2545LR,247xRD,248xRD Start
#if((_SCALER_TYPE == _RTD2545LR) || (_SCALER_TYPE == _RTD247xRD) || (_SCALER_TYPE == _RTD248xRD))
//--------------------------------------------------
// Vivid Color - YUV2RGB (Page7)
//--------------------------------------------------
#define _P7_YUV2RGB_CTRL_BF                 0xBF        // YUV2RGB Control
#define _P7_YUV2RGB_ACCESS_C0               0xC0        // YUV2RGB Coefficient Access Port
#define _P7_YUV2RGB_COEF_DATA_C1            0xC1        // YUV2RGB Coefficient Data Port
//Address: P7-C2 ~ P7-C6 Reserved
#endif // End of #if((_SCALER_TYPE == _RTD2545LR) || (_SCALER_TYPE == _RTD247xRD) || (_SCALER_TYPE == _RTD248xRD))
//Anderson 071220 for 2545LR,247xRD,248xRD End

//--------------------------------------------------
// Vivid Color - DCC (Page7)
//--------------------------------------------------
#define _P7_DCC_CTRL0_C7                    0xC7        // DCC Control Register 0
#define _P7_DCC_CTRL1_C8                    0xC8        // DCC Control Register 1
#define _P7_DCC_ACCESS_PORT_C9              0xC9        // DCC Access Port
#define _P7_DCC_DATA_PORT_CA                0xCA        // DCC Data Port
//Address: P7-CB ~ P7-CF Reserved

//--------------------------------------------------
// Vivid Color - ICM (Page7)
//--------------------------------------------------
#define _P7_ICM_CTRL_D0                     0xD0        // ICM Control Register
#define _P7_ICM_SEL_D1                      0xD1        // ICM Accessing Through Data Port Select
#define _P7_ICM_ACCESS_PORT_D2              0xD2        // ICM Access Port
#define _P7_ICM_DATA_PORT_D3                0xD3        // ICM Data Port
//Address: P7-D4 ~ P7-D5 Reserved
#define _P7_PKING_ACCESS_PORT_D6            0xD6        // Y Peaking Coring Access Port
#define _P7_PKING_DATA_PORT_D7              0xD7        // Y Peaking Coring Data Port
#define _P7_DCR_ACCESS_PORT_D8              0xD8        // DCR Access Port
#define _P7_DCR_DATA_PORT_D9                0xD9        // DCR Data Port
//Address: P7-DA ~ P7-EF Reserved

//Anderson 071220 for D Domain Random Gen. Start
//--------------------------------------------------
// Vivid Color - Pattern Gen. in D Domain (Page7)
//--------------------------------------------------
#define _P7_DISP_PG_R_CTRL_F0               0xF0        // Display Pattern Gen. R Control
#define _P7_DISP_PG_G_CTRL_F1               0xF1        // Display Pattern Gen. G Control
#define _P7_DISP_PG_B_CTRL_F2               0xF2        // Display Pattern Gen. B Control
#define _P7_DISP_PG_R_INITIAL_F3            0xF3        // Display Pattern Gen. R Initial Value
#define _P7_DISP_PG_G_INITIAL_F4            0xF4        // Display Pattern Gen. G Initial Value
#define _P7_DISP_PG_B_INITIAL_F5            0xF5        // Display Pattern Gen. B Initial Value
#define _P7_DISP_PG_PIXEL_DELTA_F6          0xF6        // Pixel Delta Value for Incremental
#define _P7_DISP_PG_LINE_DELTA_F7           0xF7        // Line Delta Value for Incremental
#define _P7_DISP_PG_PIXEL_STEP_MSB_F8       0xF8        // Pixel Step for Toggle/Incremental(MSB)
#define _P7_DISP_PG_LINE_STEP_MSB_F9        0xF9        // Line Step for Toggle/Incremental(MSB)
#defi