scalerdef.h

realtek LCD monitor, TV开发源代码

//--------------------------------------------------
// Auto Black Level (Page0)
//--------------------------------------------------
#define _P0_ABL_CTRL1_E2                    0xE2        // Auto Black Level Control Register1
#define _P0_ABL_CTRL2_E3                    0xE3        // Auto Black Level Control Register2
#define _P0_ABL_CTRL3_E4                    0xE4        // Auto Black Level Control Register3
#define _P0_ABL_CTRL4_E5                    0xE5        // Auto Black Level Control Register4
#define _P0_ABL_CTRL5_E6                    0xE6        // Auto Black Level Control Register5
#define _P0_ABL_CTRL6_E7                    0xE7        // Auto Black Level Control Register6
#define _P0_ABL_CTRL7_E8                    0xE8        // Auto Black Level Control Register6
//#define _P0_ABL_R_VALUE_E9                  0xE9        // Auto Black Level Value of Red Channel in Test Mode
//#define _P0_ABL_G_VALUE_EA                  0xEA        // Auto Black Level Value of Green Channel in Test Mode
//#define _P0_ABL_B_VALUE_EB                  0xEB        // Auto Black Level Value of Blue Channel in Test Mode
//#define _P0_ABL_R_NOISE_VALUE_EC            0xEC        // Auto Black Level Noise Value of Red Channel in Test Mode
//#define _P0_ABL_G_NOISE_VALUE_ED            0xED        // Auto Black Level Noise Value of Green Channel in Test Mode
//#define _P0_ABL_B_NOISE_VALUE_EE            0xEE        // Auto Black Level Noise Value of Blue Channel in Test Mode
//Address: P0-EF ~ P0-F2 Reserved

//--------------------------------------------------
// Low Voltage Reset (Page0)
//--------------------------------------------------
#define _P0_POWER_ON_RESET_F3               0xF3        // Negative Threshold Value For Power On Reset

//--------------------------------------------------
// Schmitt Trigger Control (Page0)
//--------------------------------------------------
#define _P0_HS_SCHMITT_TRIGGER_CTRL_F4      0xF4        // Schmitt Trigger Control Register
//Address: P0-F5 ~ P0-FF Reserved

//Anderson 071220 for 2545LR,247xRD,248xRD Start
#if((_SCALER_TYPE == _RTD2545LR) || (_SCALER_TYPE == _RTD247xRD) || (_SCALER_TYPE == _RTD248xRD))
//--------------------------------------------------
// Memory PLL (Page0)
//--------------------------------------------------
#define _P0_MPLL_M_F5                       0xF5        // MPLL M Code
#define _P0_MPLL_N_F6                       0xF6        // MPLL N Code
#define _P0_MPLL_CRNT_F7                    0xF7        // MPLL Current Control
#define _P0_MPLL_WD_F8                      0xF8        // MPLL WatchDog Control
#define _P0_MPLL_CAL_F9                     0xF9        // MPLL Calibration

//--------------------------------------------------
// MCLK Spread Spectrum (Page0)
//--------------------------------------------------
#define _P0_MCLK_FINE_TUNE_OFFSET_MSB_FA    0xFA        // MCLK Offset MSB
#define _P0_MCLK_FINE_TUNE_OFFSET_LSB_FB    0xFB        // MCLK Offset LSB //Anderson 080128 for Typeing Error
#define _P0_MCLK_SPREAD_SPECTRUM_FC         0xFC        // MCLK Spreading Range
#define _P0_MPLL_RESULT_FD                  0xFD        // MPLL Calibration Result
//Address: P0-FE ~ P0-FF Reserved
#endif // End of #if((_SCALER_TYPE == _RTD2545LR) || (_SCALER_TYPE == _RTD247xRD) || (_SCALER_TYPE == _RTD248xRD))
//Anderson 071220 for 2545LR,247xRD,248xRD End


/////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////Page 1: PLL////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////

//--------------------------------------------------
// DDS Setting For ADC PLL (Page1)
//--------------------------------------------------
#define _P1_PLL_DIV_CTRL_A0                 0xA0        // PLL DIV Control Register
#define _P1_I_CODE_M_A1                     0xA1        // I Code MByte
#define _P1_I_CODE_L_A2                     0xA2        // I Code LByte
#define _P1_P_CODE_A3                       0xA3        // P Code
#define _P1_PFD_CALIBRATED_RESULTS_H_A4     0xA4        // PFD Calibrated Result HByte
#define _P1_PFD_CALIBRATED_RESULTS_L_A5     0xA5        // PFD Calibrated Result LByte
#define _P1_PE_MEASURE_H_A6                 0xA6        // Phase Error Measure HByte
#define _P1_PE_MEASURE_L_A7                 0xA7        // Phase Error Measure LByte
#define _P1_PE_MAX_MEASURE_H_A8             0xA8        // Phase Error Max MEasure HByte
#define _P1_PE_MAX_MEASURE_L_A9             0xA9        // Phase Error Max MEasure LByte
#define _P1_FAST_PLL_CTRL_AA                0xAA        // Fast PLL Control Register
#define _P1_FAST_PLL_SUM_I_AB               0xAB        // Fast PLL SUM_I

//--------------------------------------------------
// ADC PLL (Page1)
//--------------------------------------------------
#define _P1_PLL_M_AC                        0xAC        // PLL M code
#define _P1_PLL_N_AD                        0xAD        // PLL N Code
#define _P1_PLL_CRNT_AE                     0xAE        // PLL Current/Resistor Register
#define _P1_PLL_WD_AF                       0xAF        // PLL Watch Dog Register
#define _P1_MIX_B0                          0xB0        // PLL Mix Register
#define _P1_PLLDIV_H_B1                     0xB1        // PLL DIV HByte
#define _P1_PLLDIV_L_B2                     0xB2        // PLL DIV LByte
//#define _P1_PLLPHASE_CTRL0_B3               0xB3        // PLL Phase Control Register0
#define _P1_PLLPHASE_CTRL1_B4               0xB4        // PLL Phase Control Register1
#define _P1_PLL_PHASE_INTERPOLATION_B5      0xB5        // PLL Phase Interpolation
#define _P1_P_CODE_MAPPING_METHOD_B6        0xB6        // P Code Mapping Method
#define _P1_PE_TRACKING_METHOD_B7           0xB7        // PE Tracking Method
#define _P1_DDS_MIX_1_B8                    0xB8        // DDS Mix 1
#define _P1_DDS_MIX_2_B9                    0xB9        // DDS Mix 2
#define _P1_DDS_MIX_3_BA                    0xBA        // DDS Mix 3
#define _P1_DDS_MIX_4_BB                    0xBB        // DDS Mix 4
#define _P1_DDS_MIX_5_BC                    0xBC        // DDS Mix 5
//#define _P1_DDS_MIX_6_BD                    0xBD        // DDS Mix 6
//#define _P1_DDS_MIX_7_BE                    0xBE        // DDS Mix 7

//--------------------------------------------------
// DPLL (Page1)
//--------------------------------------------------
#define _P1_DPLL_M_BF                       0xBF        // DPLL M Divider
#define _P1_DPLL_N_C0                       0xC0        // DPLL N Divider
#define _P1_DPLL_CRNT_C1                    0xC1        // DPLL Current/Resistor Register

//--------------------------------------------------
// DCLK Spread Spectrum (Page1)
//--------------------------------------------------
#define _P1_DPLL_WD_C2                      0xC2        // DPLL Watch Dog Register
//Anderson 071220 for 2545LR,247xRD,248xRD Start
#if(_SCALER_TYPE == _RTD2472D)
#define _P1_DPLL_OTHER_C3                   0xC3        // DPLL Other Register
#elif((_SCALER_TYPE == _RTD2545LR) || (_SCALER_TYPE == _RTD247xRD) || (_SCALER_TYPE == _RTD248xRD))
#define _P1_DPLL_CAL_C3                     0xC3        // DPLL Calibration
#else
   No Setting !
#endif //End of #if(_SCALER_TYPE == _RTD2472D)
//Anderson 071220 for 2545LR,247xRD,248xRD End
#define _P1_DCLK_FINE_TUNE_OFFSET_MSB_C4    0xC4        // Display Clock Fine Tune Offset MSB
#define _P1_DCLK_FINE_TUNE_OFFSET_LSB_C5    0xC5        // Display Clock Fine Tune Offset LSB
#define _P1_DCLK_SPREAD_SPECTRUM_C6         0xC6        // Display Clock Spread Spectrum
#define _P1_EVEN_FIX_LASTLINE_DVTOTAL_M_C7  0xC7        // Even Fixed Last Line MSB //Anderson 071220 for Typing Error
#define _P1_EVEN_FIX_LASTLINE_DVTOTAL_L_C8  0xC8        // Even Fixed Last Line DVTotal LSB
#define _P1_EVEN_FIX_LASTLINE_LENGTH_L_C9   0xC9        // Even Fixed Last Line Length LSB
#define _P1_EVEN_FIXED_LAST_LINE_CTRL_CA    0xCA        // Fixed Last Line Control Register
//#define _P1_ODD_FIX_LASTLINE_DVTOTAL_M_CB           0xCB        // Odd Fixed Last Line MSB //Anderson 071220 for Typing Error
//#define _P1_ODD_FIX_LASTLINE_DVTOTAL_L_CC   0xCC        // Odd Fixed Last Line DVTotal LSB
#if(_SCALER_TYPE == _RTD2472D)//cyyeh 20080519
#define _P1_ODD_FIX_LASTLINE_LENGTH_L_CD    0xCD        // Odd Fixed Last Line Length LSB //cyyeh 20080519
#define _P1_DCLK_SPREAD_SPECTRUM_CE         0xCE        // Dclk Spread Spectrum
#define _P1_PHASE_RESULT_MSB_CF             0xCF        // Phase Result MSB
#elif((_SCALER_TYPE == _RTD2545LR) || (_SCALER_TYPE == _RTD247xRD) || (_SCALER_TYPE == _RTD248xRD))
#define _P1_MCLK_FINE_TUNE_OFFSET_MSB_CD       0xCD        // Mclk offset MSB
#define _P1_MCLK_FINE_TUNE_OFFSET_LSB_CE       0xCE        // Mclk offset LSB
#define _P1_MCLK_SPREAD_SPECTRUM_CF            0xCF        // Mclk Spread Spectrum
#else
   No Setting !!
#endif //End of #if(_SCALER_TYPE == _RTD2472D)

//#define _P1_PHASE_LINE_LSB_D0               0xD0        // Phase Line LSB
//#define _P1_PHASE_PIXEL_LSB_D1              0xD1        // Phase Pixel LSB
//#define _P1_TARGET_DCLK_TUNE_OFFSET_MSB_D2  0xD2        // Target Dclk Tune Offset MSB
//#define _P1_TARGET_DCLK_TUNE_OFFSET_LSB_D3  0xD3        // Target Dclk Tune Offset LSB
//Address: P1-D4 ~ P1-DF Reserved
//Anderson 071220 for 2545LR,247xRD,248xRD Start
#if((_SCALER_TYPE == _RTD2545LR) || (_SCALER_TYPE == _RTD247xRD) || (_SCALER_TYPE == _RTD248xRD))
#define _P1_DPLL_RESULT_D4                  0xD4        // DPLL Calibration Result
//Address: P1-D5 ~ P1-DF Reserved
#endif
//Anderson 071220 for 2545LR,247xRD,248xRD End

//--------------------------------------------------
// Multiply PLL For Input Crystal (Page1)
//--------------------------------------------------
//Anderson 071220 for 2545LR,247xRD,248xRD Start
#if(_SCALER_TYPE == _RTD2472D)
#define _P1_MULTIPLY_PLL_CTRL0_E0           0xE0        // M2PLL Control Register0
#define _P1_MULTIPLY_PLL_CTRL1_E1           0xE1        // M2PLL Control Register1
//#define _P1_RESERVED_E2                     0xE2        // P1 Reserved E2
//#define _P1_RESERVED_E3                     0xE3        // P1 Reserved E3
#define _P1_MULTIPLY_PLL_CTRL2_E4           0xE4        // M2PLL Control Register2
#define _P1_MULTIPLY_PLL_CTRL3_E5           0xE5        // M2PLL Control Register3
#elif((_SCALER_TYPE == _RTD2545LR) || (_SCALER_TYPE == _RTD247xRD) || (_SCALER_TYPE == _RTD248xRD))
#define _P1_M2PLL_M_E0                      0xE0        // M2PLL M Code
#define _P1_M2PLL_N_E1                      0xE1        // M2PLL N Code
//#define _P1_RESERVED_E2                     0xE2        // P1 Reserved E2
//#define _P1_RESERVED_E3                     0xE3        // P1 Reserved E3
#define _P1_M2PLL_CRNT_E4                   0xE4        // M2PLL Curent Control
#define _P1_M2PLL_WD_E5                     0xE5        // M2PLL Watch Dog
#else
    No Setting !!
#endif //End of #if(_SCALER_TYPE == _RTD2472D)
//Address: P1-E6 ~ P1-EF Reserved
//Anderson 071220 for 2545LR,247xRD,248xRD End

//--------------------------------------------------
// Audio DAC (Page1)
//--------------------------------------------------
#define _P1_BB_POWER0_F0                    0xF0        // DAC Power Control0
#define _P1_BB_POWER1_F1                    0xF1        // DAC Power Control1
#define _P1_AIN_CTL_F2                      0xF2        // DAC AIN Control
#define _P1_DAC_CTL_F3                      0xF3        // DAC Output Volume Control
#define _P1_AOUT_CTL_F4                     0xF4        // DAC AOUT Control
#define _P1_HPOUT_CTL_F5                    0xF5        // DAC HPOUT Control
#define _P1_MBIAS_CTL0_F6                   0xF6        // DAC Bias Current Control0
#define _P1_MBIAS_CTL1_F7                   0xF7        // DAC Bias Current Control1