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📄 scalerdef.h

📁 realtek LCD monitor, TV开发源代码
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//#define _RESERVED_6B                        0x6B        // Reserved 6B

//--------------------------------------------------
// Overlay/Color Palette/Background Color Control
//--------------------------------------------------
#define _OVERLAY_CTRL_6C                    0x6C        // Overlay Display Control Register
#define _BGND_COLOR_CTRL_6D                 0x6D        // Background Color Control Register
#define _OVERLAY_LUT_ADDR_6E                0x6E        // Overlay Look Up Table (LUT) Address
#define _COLOR_LUT_PORT_6F                  0x6F        // Color LUT Access Port

//--------------------------------------------------
// Image Auto Function
//--------------------------------------------------
#define _H_BOUNDARY_H_70                    0x70        // Horizontal Start/End Boundary HByte
#define _H_BOUNDARY_STA_L_71                0x71        // Horizontal Start Boundary HByte
#define _H_BOUNDARY_END_L_72                0x72        // Horizontal End Boundary HByte
#define _V_BOUNDARY_H_73                    0x73        // Vertical Start/End Boundary HByte
#define _V_BOUNDARY_STA_L_74                0x74        // Vertical Start Boundary LByte
#define _V_BOUNDARY_END_L_75                0x75        // Vertical End Boundary LByte
#define _RED_NOISE_MARGIN_76                0x76        // Red Noise Margin Control Register
#define _GRN_NOISE_MARGIN_77                0x77        // Green Noise Margin Control Register
#define _BLU_NOISE_MARGIN_78                0x78        // Blue Noise Margin Control Register
#define _DIFF_THRESHOLD_79                  0x79        // Difference Threshold
#define _AUTO_ADJ_CTRL0_7A                  0x7A        // Auto Adjusting Control Register 0
#define _HW_AUTO_PHASE_CTRL0_7B             0x7B        // Hardware Auto Phase Control Register 0
#define _HW_AUTO_PHASE_CTRL1_7C             0x7C        // Hardware Auto Phase Control Register 1
#define _AUTO_ADJ_CTRL1_7D                  0x7D        // Auto Adjusting Control Register 1
#define _V_START_END_H_7E                   0x7E        // Active Region Vertical Start/End HByte
#define _V_START_L_7F                       0x7F        // Active Region Vertical Start LByte
#define _V_END_L_80                         0x80        // Active Region Vertical End LByte
#define _H_START_END_H_81                   0x81        // Active Region Horizontal Start/End HByte
#define _H_START_L_82                       0x82        // Active Region Horizontal Start LByte
#define _H_END_L_83                         0x83        // Active Region Horizontal End LByte
#define _AUTO_PHASE_3_84                    0x84        // Auto Phase Result Register Byte 3
#define _AUTO_PHASE_2_85                    0x85        // Auto Phase Result Register Byte 2
#define _AUTO_PHASE_1_86                    0x86        // Auto Phase Result Register Byte 1
#define _AUTO_PHASE_0_87                    0x87        // Auto Phase Result Register Byte 0

//Anderson 071220 for 2545LR,247xRD,248xRD Start
//--------------------------------------------------
// Dithering Control (I domain)
//--------------------------------------------------
#if((_SCALER_TYPE == _RTD2545LR) || (_SCALER_TYPE == _RTD247xRD) || (_SCALER_TYPE == _RTD248xRD))
#define _DITHERING_DATA_ACCESS_88           0x88        // Dithering Table DATA ACCESS (I Domain)
#define _DITHERING_CTRL1_89                 0x89        // Dithering Control Register
#endif
//Anderson 071220 for 2545LR,247xRD,248xRD End
//#define _RESERVED_88                        0x88        // Reserved 88
//#define _RESERVED_89                        0x89        // Reserved 89
//#define _RESERVED_8A                        0x8A        // Reserved 8A

//--------------------------------------------------
// Embedded Timing Controller(Port)
//--------------------------------------------------
#define _TCON_ADDR_PORT_8B                  0x8B        // TCON Address Port for Embedded TCON Access
#define _TCON_DATA_PORT_8C                  0x8C        // TCON Data Port for Embedded TCON Access

//--------------------------------------------------
// Pin Configuration & Test Function(Port)
//--------------------------------------------------
#define _PS_ACCESS_PORT_8D                  0x8D        // Pin Share Access Port
#define _PS_DATA_PORT_8E                    0x8E        // Pin Share Data Port
//#define _RESERVED_8F                        0x8F        // Reserved 8F

//--------------------------------------------------
// Embedded OSD
//--------------------------------------------------
#define _OSD_ADDR_MSB_90                    0x90        // OSD Address MSB
#define _OSD_ADDR_LSB_91                    0x91        // OSD Address LSB
#define _OSD_DATA_PORT_92                   0x92        // OSD Data Port
#define _OSD_SCRAMBLE_93                    0x93        // OSD Scramble
#define _OSD_TEST_94                        0x94        // OSD Test
//#define _RESERVED_95                        0x95        // Reserved 95
//#define _RESERVED_96                        0x96        // Reserved 96
//#define _RESERVED_97                        0x97        // Reserved 97

//--------------------------------------------------
// Digital Filter
//--------------------------------------------------
#define _DIGITAL_FILTER_CTRL_98             0x98        // Digital Filter Control Register
#define _DIGITAL_FILTER_PORT_99             0x99        // Digital Filter Port

//--------------------------------------------------
// VBI(Port)
//--------------------------------------------------
//Anderson 071220 for 2545LR Start
#if((_SCALER_TYPE == _RTD2472D) || (_SCALER_TYPE == _RTD247xRD) || (_SCALER_TYPE == _RTD248xRD))
#define _VBI_ACCESS_PORT_9A                 0x9A        // VBI Access Port
#define _VBI_DATA_PORT_9B                   0x9B        // VBI Data Port
#endif
//Anderson 071220 for 2545LR End

//--------------------------------------------------
// Video Color Space Conversion
//--------------------------------------------------
//Anderson 071220 for 2545LR,247xRD,248xRD Start
#if(_SCALER_TYPE == _RTD2472D)
#define _YUV2RGB_CTRL_9C                    0x9C        // YUV to RGB Control Register
#define _YUV_RGB_ACCESS_9D                  0x9D        // YUV to RGB Access
#define _YUV_RGB_COEF_DATA_9E               0x9E        // YUV to RGB Coefficient Data Port
#elif((_SCALER_TYPE == _RTD2545LR) || (_SCALER_TYPE == _RTD247xRD) || (_SCALER_TYPE == _RTD248xRD))
#define _YUV_RGB_CTRL_9C                    0x9C        // YUV<->RGB Control Register //Anderson 080107 typing error
#define _YUV_RGB_COEF_DATA_9D               0x9D        // YUV<->RGB Coefficient Data
//#define _RESERVED_9E                        0x9E        // Reserved 9E
#else
   No Setting !!
#endif//End of #if(_SCALER_TYPE == _RTD2472D)
//Anderson 071220 for 2545LR,247xRD,248xRD End

//OLD
//--------------------------------------------------
// Peaking Filter and Coring Control(Port)
//--------------------------------------------------
#define _PC_ACCESS_PORT_9A                  0x9A        // Peaking/Coring Access Port
#define _PC_DATA_PORT_9B                    0x9B        // Peaking/Coring Data Port


//##############################################################################################//
//##############################################################################################//
//##########################################     PAGE     ######################################//
//##############################################################################################//
//##############################################################################################//

//--------------------------------------------------
// Paged Control Register
//--------------------------------------------------
#define _PAGE_SELECT_9F                     0x9F        // Page Selector (CR[A0] ~ CR[FF])

/////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////Page 0: Embedded ADC///////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////
//--------------------------------------------------
// ADC (Page0)
//--------------------------------------------------
#define _P0_ADC_POWER_SOG_SOY_CTL_BA        0xBA        // ADC Power for SOG /SOY
#define _P0_ADC_2X_SAMPLE_BB                0xBB        // ADC 2X Sample Clock Select //Anderson 071220 for typeing error
#define _P0_ADC_CLOCK_BC                    0xBC        // ADC Clock Output Select
#define _P0_ADC_TEST_BD                     0xBD        // ADC Test Function
#define _P0_ADC_RGB_GAIN_LSB_BE             0xBE        // ADC RGB Gain LSB
#define _P0_ADC_RGB_OFFSET_LSB_BF           0xBF        // ADC RGB Offset LSB
#define _P0_RED_GAIN_C0                     0xC0        // ADC Red Channel Gain Adjust
#define _P0_GRN_GAIN_C1                     0xC1        // ADC Green Channel Gain Adjust
#define _P0_BLU_GAIN_C2                     0xC2        // ADC Blue Channel Gain Adjust
#define _P0_RED_OFFSET_C3                   0xC3        // ADC Red Channel Offset Adjust
#define _P0_GRN_OFFSET_C4                   0xC4        // ADC Green Channel Offset Adjust
#define _P0_BLU_OFFSET_C5                   0xC5        // ADC Blue Channel Offset Adjust
#define _P0_ADC_POWER_C6                    0xC6        // ADC Power Control Register
#define _P0_ADC_I_BAIS0_C7                  0xC7        // ADC Bais Current Control Register0
#define _P0_ADC_I_BAIS1_C8                  0xC8        // ADC Bais Current Control Register1
#define _P0_ADC_I_BAIS2_C9                  0xC9        // ADC Bais Current Control Register2
#define _P0_ADC_I_BAIS3_CA                  0xCA        // ADC Bais Current Control Register3
#define _P0_ADC_I_BAIS4_CB                  0xCB        // ADC Bais Current Control Register4
#define _P0_ADC_V_BIAS0_CC                  0xCC        // ADC Bais Voltage Control Register0
#define _P0_ADC_V_BIAS1_CD                  0xCD        // ADC Bais Voltage Control Register1
#define _P0_ADC_RGB_CTRL_CE                 0xCE        // ADC RGB Control Register //Anderson 071220 for typeing error
#define _P0_ADC_RED_CTL_CF                  0xCF        // ADC Red Channel Control Register
#define _P0_ADC_GREEN_CTL_D0                0xD0        // ADC Green Channel Control Register
#define _P0_ADC_BLUE_CTL_D1                 0xD1        // ADC Blue Channel Control Register
#define _P0_ADC_SOG_CMP_D2                  0xD2        // ADC SOG Input Mux Select
#define _P0_ADC_DCR_CTRL_D3                 0xD3        // ADC DCR Reference Control Register
#define _P0_ADC_CLAMP_CTRL0_D4              0xD4        // ADC Clamp Control Register0
#define _P0_ADC_CLAMP_CTRL1_D5              0xD5        // ADC Clamp Control Register1
#define _P0_ADC_CLAMP_CTRL2_D6              0xD6        // ADC Clamp Control Register2
//Anderson 071220 for 2545LR,247xRD,248xRD Start
#if((_SCALER_TYPE == _RTD2545LR) || (_SCALER_TYPE == _RTD247xRD) || (_SCALER_TYPE == _RTD248xRD))
#define _P0_ADC_SOG_DAC_SOY_CONTROL_D7      0xD7        // ADC SOG0 DAC Control
#define _P0_TEST_PTN_POS_H_D8               0xD8        // Test Pattern H/V Position HByte
#define _P0_TEST_PTN_VPOS_L_D9              0xD9        // Assign the test pattern digitized position(LByte) in line after V_Start.
#define _P0_TEST_PTN_HPOS_L_DA              0xDA        // Assign the test pattern digitized position(LByte) in line after H_Start.
#define _P0_TEST_PTN_RD_DB                  0xDB        // Test Pattern Red Channel Digitized Result
#define _P0_TEST_PTN_GD_DC                  0xDC        // Test Pattern Green Channel Digitized Result
#define _P0_TEST_PTN_BD_DD                  0xDD        // Test Pattern Blue Channel Digitized Result
#define _P0_TEST_PTN_CTRL_DE                0xDE        // Test Pattern Control
#if(_SCALER_TYPE == _RTD2545LR)
#define _P0_EBD_REGLATOR_VOL_DF             0xDF        // Embedded Regulator Control
#endif
#endif
//Anderson 071220 for 2545LR,247xRD,248xRD End
//#define _P0_TEST_PTN_POS_H_D7               0xD7        // Test Pattern H/V Position HByte
//#define _P0_TEST_PTN_VPOS_L_D8              0xD8        // Assign the test pattern digitized position(LByte) in line after V_Start.
//#define _P0_TEST_PTN_HPOS_L_D9              0xD9        // Assign the test pattern digitized position(LByte) in line after H_Start.
//#define _P0_TEST_PTN_RD_DA                  0xDA        // Test Pattern Red Channel Digitized Result
//#define _P0_TEST_PTN_GD_DB                  0xDB        // Test Pattern Green Channel Digitized Result
//#define _P0_TEST_PTN_BD_DC                  0xDC        // Test Pattern Blue Channel Digitized Result

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