adjust.h

realtek LCD monitor, TV开发源代码

//**********************************************************************************************************
//  The  Software  is  proprietary,  confidential,  and  valuable to Realtek Semiconductor
//  Corporation  ("Realtek").  All  rights, including but not limited  to  copyrights,
//  patents,  trademarks, trade secrets, mask work rights, and other similar rights and interests,
//  are reserved to Realtek. Without  prior  written  consent  from  Realtek,  copying, reproduction,
//  modification,  distribution,  or  otherwise  is strictly prohibited. The Software  shall  be
//  kept  strictly  in  confidence,  and  shall  not be  disclosed to or otherwise accessed by
//  any third party. @ <2003> - <2008>   The Software is provided "AS IS" without any warranty of any kind,
//  express, implied, statutory or otherwise.
//**********************************************************************************************************
//----------------------------------------------------------------------------------------------------
// ID Code      : Adjust.h No.0000
// Update Note  :
//----------------------------------------------------------------------------------------------------

//--------------------------------------------------
// Definitions of Digital Filter
//--------------------------------------------------
#define _DISABLE_PORT                   0
#define _PHASE_ACCESS_PORT              1
#define _NEG_SMEAR_ACCESS_PORT          2
#define _POS_SMEAR_ACCESS_PORT          3
#define _NEG_RING_ACCESS_PORT           4
#define _POS_RING_ACCESS_PORT           5
#define _MISMATCH_ACCESS_PORT           6
#define _YPBPR_ACCESS_PORT              7
#define _NOISE_REDUCTION_PORT           8

#define _YPBPR_DISABLE                  0
#define _YPBPR_ENABLE                   7

#define _FUNCTION_DISABLE               0
#define _FUNCTION_ENABLE                1

#define _PHASE_THD_0                    0
#define _PHASE_THD_1                    1
#define _PHASE_THD_2                    2
#define _PHASE_THD_3                    3
#define _PHASE_THD_4                    4
#define _PHASE_THD_5                    5
#define _PHASE_THD_6                    6
#define _PHASE_THD_7                    7

#define _SMEAR_RING_THD_0               0
#define _SMEAR_RING_THD_1               1
#define _SMEAR_RING_THD_2               2
#define _SMEAR_RING_THD_3               3
#define _SMEAR_RING_THD_4               4
#define _SMEAR_RING_THD_5               5
#define _SMEAR_RING_THD_6               6
#define _SMEAR_RING_THD_7               7

#define _MISMATCH_THD_0                 0
#define _MISMATCH_THD_1                 1

#define _NOISE_REDUCTION_THD_0          0
#define _NOISE_REDUCTION_THD_1          1
#define _NOISE_REDUCTION_THD_2          2
#define _NOISE_REDUCTION_THD_3          3
#define _NOISE_REDUCTION_THD_4          4
#define _NOISE_REDUCTION_THD_5          5
#define _NOISE_REDUCTION_THD_6          6
#define _NOISE_REDUCTION_THD_7          7

#define _DIV_VALUE_0                    0
#define _DIV_VALUE_1                    1
#define _DIV_VALUE_2                    2
#define _DIV_VALUE_3                    3


//--------------------------------------------------
// Definitions of Coring Type
//--------------------------------------------------
#define _CORING_MIN                     3   // (0~5)
#define _CORING_MAX_POS                 50  // (50~60)
#define _CORING_MAX_NEG                 -50 // (-50~-60)


//--------------------------------------------------
// Definitions of Gamma Table Type
//--------------------------------------------------
#define _COMPACT_GAMMA_NORMAL_TABLE     0
#define _FULL_GAMMA_NORMAL_TABLE        1
#define _COMPACT_GAMMA_COMPRESS_TABLE   2
#define _FULL_GAMMA_COMPRESS_TABLE      3


//--------------------------------------------------
// Definitions of Dithering Type
//--------------------------------------------------
#define _INPUT_DITHER                   0
#define _OUTPUT_DITHER                  1


//--------------------------------------------------
// Definitions of TMDS Measurement
//--------------------------------------------------
#define _TMDS_MEASURE_HSYNC_BE          0x00
#define _TMDS_MEASURE_HSYNC_AF          0x01
#define _TMDS_MEASURE_DE_BE             0x02
#define _TMDS_MEASURE_DE_AF             0x03

#define _TMDS_MEASURE_AVE               0x00
#define _TMDS_MEASURE_MAX               0x01
#define _TMDS_MEASURE_MIN               0x02

#define _MEASURE_HSYNC                  0
#define _MEASURE_DE                     1


//--------------------------------------------------
// Definations of Watch Dogs
//--------------------------------------------------
#define _WD_DV_TIMEOUT                  0x20
#define _WD_APLL_NONLOCK                0x10
#define _WD_FRAMESYNC                   0x08
#define _WD_IH_IV_ERROR                 0x80
#define _WD_IH_IV_TIMEOUT_OVERFLOW      0x40
// V010 Patch Note (30) : Add APLL New Mode Setting
#if(_WD_APLL == _ON)

#define _WD_DV_TIMEOUT_APLL_NONLOCK     (_WD_DV_TIMEOUT | _WD_APLL_NONLOCK)
#define _WD_FRAMESYNC_APLL_NONLOCK      (_WD_APLL_NONLOCK | _WD_FRAMESYNC)
#define _WD_INPUT_SYNC_ERROR            (_WD_IH_IV_ERROR | _WD_IH_IV_TIMEOUT_OVERFLOW)
#define _WD_ALL                         (_WD_DV_TIMEOUT | _WD_APLL_NONLOCK | _WD_FRAMESYNC | _WD_INPUT_SYNC_ERROR)

#else

#define _WD_DV_TIMEOUT_APLL_NONLOCK     (_WD_DV_TIMEOUT | 0)
#define _WD_FRAMESYNC_APLL_NONLOCK      (0 | _WD_FRAMESYNC)
#define _WD_INPUT_SYNC_ERROR            (_WD_IH_IV_ERROR | _WD_IH_IV_TIMEOUT_OVERFLOW)
#define _WD_ALL                         (_WD_DV_TIMEOUT | 0 | _WD_FRAMESYNC | _WD_INPUT_SYNC_ERROR)

#endif

//--------------------------------------------------
// Definations of HDMI Watch Dog Control
//--------------------------------------------------
#define _WD_SET_AVMUTE_ENABLE           0x01
#define _WD_AUDIO_FOR_TMDS_CLOCK        0x02
#define _WD_PACKET_VARIATION            0x04
#define _WD_AUDIO_FIFO                  0x08
#define _WD_HDMI_ALL                    (_WD_SET_AVMUTE_ENABLE | _WD_AUDIO_FOR_TMDS_CLOCK | _WD_PACKET_VARIATION | _WD_AUDIO_FIFO)

//--------------------------------------------------
// Definations of APLL _G_VALUE_DIVIDER ,//yc 20080225
//--------------------------------------------------
#define _G_VALUE_DIVIDER_0              4
#define _G_VALUE_DIVIDER_1              16
#define _G_VALUE_DIVIDER_2              64
#define _G_VALUE_DIVIDER_3              128
#define _G_VALUE_DIVIDER_4              256
#define _G_VALUE_DIVIDER_5              512

#if(_NEW_ADC == _TRUE)
// V010 Patch Note (1) : Adjust ADC Clock Modify
//--------------------------------------------------
// Definations of Adjust ADC Clock Control
//--------------------------------------------------
#define _APLL_INITIAL                   0
#define _APLL_FAST_LOCK                 1
#endif



#ifdef __ADJUST__


//--------------------------------------------------
// Global Variables
//--------------------------------------------------
BYTE idata ucAdjustCtrl         = 0;
WORD idata usPEValue            = 120;

#if(_NEW_ADC == _FALSE)
// V010 Patch Note (1) : Adjust ADC Clock Modify
DWORD idata ulPllDivider;
DWORD idata ulPllDividerRem;
DWORD idata ulIHFreqApllFast;
SWORD sAdjustHue;
SWORD sAdjustSat;

#else

WORD idata g_ulPllIHTotal = 0;
DWORD idata g_ulPllDivider = 0;
SWORD idata sAdjustHue = 0;
SWORD idata sAdjustSat = 0;

#endif

#if(_AUDIO_SUPPORT == _ON)
BYTE xdata HdmiAudioOutPort     = 0x00;
bit HdmiAudioDetect             = 0x00;
#endif

//--------------------------------------------------
// Function Prototypes
//--------------------------------------------------
#if(_NEW_ADC == _FALSE)
// V010 Patch Note (1) : Adjust ADC Clock Modify
void CAdjustAdcClock(WORD usClock, BYTE ucControl);
void CAdjustAPLLFastLock(WORD usClock);
void CAdjustAdcClock_OSD(WORD usClock);
BYTE CAdjustGetAPLLSetting(WORD usClock);

#else

bit CAdjustAdcClock(WORD usClock);
bit CAdjustAPLLInitial(WORD usClock);
bit CAdjustAPLLInitial_2(WORD usClock);
bit CAdjustAPLLFastLock(WORD usClock);
BYTE CAdjustGetAPLLGValue(WORD *pDelta);

#endif

void CAdjustIHSDelay(WORD usIHSDelay);
void CAdjustIVSDelay(WORD usIVSDelay);
void CAdjustDclkOffset(WORD usDclkOffset);
void CAdjustDclkSpreadSpectrumRange(BYTE ucSpreadRange);

#if((_SCALER_TYPE == _RTD2545LR) || (_SCALER_TYPE == _RTD247xRD) || (_SCALER_TYPE == _RTD248xRD))
void CAdjustMclkOffset(WORD usMclkOffset);
void CAdjustMclkSpreadSpectrumRange(BYTE ucSpreadRange);
void CAdjustSdramPhase(BYTE *pSdramPhaseTable);
void CAdjustOdFrcPerformance(void);
#endif

void CAdjustSyncProcessorMeasureStart(void);
void CAdjustTMDSErrorCorrectionOn(void);
void CAdjustTMDSErrorCorrectionOff(void);
BYTE CAdjustTMDSMeasure(BYTE ucType, BYTE ucSelect);
DWORD CAdjustTMDSCRCMeasure(void);
void CAdjustTMDSCRCCheck(void);
BYTE CAdjustTMDSEqualizerCheck(BYTE ucPar);
bit  CAdjustTMDSEqualizer(void);
BYTE CAdjustTMDSCRC(BYTE *pArray);
void CAdjustSetDigitalCapture(void);
void CAdjustTMDSCaptureCheck(void);
void CAdjustEnableWatchDog(BYTE ucPar);
void CAdjustDisableWatchDog(BYTE ucPar);
void CAdjustEnableHDMIWatchDog(BYTE ucPar);
void CAdjustDisableHDMIWatchDog(BYTE ucPar);

void CAdjustSRGB(void);

#if(_HDCP_SUPPORT == _ON)
void CAdjustHDCP(void);
#endif

#if(_GAMMA_FUCTION == _ON)
#if(_SCALER_TYPE == _RTD2472D)
void CAdjustGamma(BYTE ucGammaTableType, BYTE *pGammaTableArrayR, BYTE *pGammaTableArrayG, BYTE *pGammaTableArrayB);

#elif((_SCALER_TYPE == _RTD2545LR) || (_SCALER_TYPE == _RTD247xRD) || (_SCALER_TYPE == _RTD248xRD))
void CAdjustLUTGamma(BYTE *pGammaTableArrayR, BYTE *pGammaTableArrayG, BYTE *pGammaTableArrayB); //20080422 +Sharon

#else
    No Setting !!

#endif // End of #if(_SCALER_TYPE == _RTD2472D)
#endif // End of #if(_GAMMA_FUCTION == _ON)

#if(_SCALER_TYPE == _RTD2472D)
void CAdjustDither(BYTE *pDitherSeqTable, BYTE * pDitherTable ,BYTE *pDitherTempoffsetTable);

#elif((_SCALER_TYPE == _RTD2545LR) || (_SCALER_TYPE == _RTD247xRD) || (_SCALER_TYPE == _RTD248xRD))
void CAdjustDither(BYTE *pDitherSeqTable, BYTE * pDitherTable, BYTE *pDitherTempoffsetTable, bit bDitherType);