📄 casio25.c
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#include "ssd192X.h"
int LCD_WIDTH=160;
int LCD_HEIGHT=240;
int WIDE_TFT=0;void lcd_hw_init(void)
{
int i=0;
INT32 lcd_hw_init[][2]=
{
{REG_PCLK_FREQ_RATIO_0 ,0xff},//0x158
{REG_PCLK_FREQ_RATIO_1 ,0xff},//0x159
{REG_PCLK_FREQ_RATIO_2 ,0x00},//0x15a
{REG_PANEL_TYPE ,0x72},//0x10//serial tft {REG_MOD_RATE ,0x00},//0x11
{REG_HORIZ_TOTAL_0 ,0x18},//0x12
{REG_HORIZ_TOTAL_1 ,0x07},//0x13
{REG_HDP ,0x15},//0x14
{REG_HDP_START_POS0 ,0x0a},//0x16
{REG_HDP_START_POS1 ,0x00},//0x17
{REG_VERT_TOTAL0 ,0xef},//0x18
{REG_VERT_TOTAL1 ,0x00},//0x19
{REG_VDP0 ,0xdb},//0x1C
{REG_VDP1 ,0x00},//0x1D
{REG_VDP_START_POS0 ,0x03},//0x1e
{REG_VDP_START_POS1 ,0x00},//0x1f
{REG_HSYNC_PULSE_WIDTH ,0x81},//0x20
{REG_HSYNC_PULSE_START_POS0 ,0x00},//0x22
{REG_HSYNC_PULSE_START_POS1 ,0x00},//0x23
{REG_VSYNC_PULSE_WIDTH ,0x80},//0x24
{REG_VSYNC_PULSE_START_POS0 ,0x00},//0x26
{REG_VSYNC_PULSE_START_POS1 ,0x00},//0x27
{REG_GPIO_STATUS_CONTROL1 ,0x00},//0xac
{REG_HRTFT_SPECIAL_OUTPUT ,0x01},//0x38
{REG_DISPLAY_MODE ,0xC4},//0x70
{REG_DV_OFORMAT ,0x00},//0x1a4
{REG_HORIZ_TOTAL_0 ,0x15},//0x12
{REG_HORIZ_TOTAL_1 ,0x07},//0x13
{REG_HDP ,0x13},//0x14
{REG_HDP_START_POS0 ,0x04},//0x16
{REG_VERT_TOTAL0 ,240},//0x18
{REG_VDP0 ,239},//0x1c
{REG_VDP_START_POS0 ,0},//0x1e
{REG_FPFRAME_START_OFFSET0 ,1},//0x30
{REG_HSYNC_PULSE_START_POS0 ,1},//0x22
// {REG_MAIN_WIN_ADDR_OFFSET0 ,0x50},//0x78
// {REG_MAIN_WIN_DISP_START_ADDR0 ,0x00},//0x74
// {REG_SPECIAL_EFFECTS ,0x40},//0x71
{REG_DV_FRAME_SAMPLING, 0x01},//0x161
{REG_LLINE_PULSE_START_SUBPIXEL_POS, 0x03},//0x21=3pixels {REG_LCD_SUBPIXEL_ALIGNMENT, 0x18},//0x42=GBR/RGB {REG_DV_SUBPIXEL_MODE, 0x02}, //0x1a5=enable subpixel accurate horizontal decimation in DV and set "1st row inside,2nd row outside"=0x02 {REG_DEFINE_END ,0x00}//0xFFFF
};
debug("Initialize CASIO 2.5\" Panel\n");
while(lcd_hw_init[i][0]!=REG_DEFINE_END)
{
SSD_REGWB(lcd_hw_init[i][0],lcd_hw_init[i][1]);
i++;
}
debug("send hdips\n");
//hdisp
//bit 3= DI; bit 2=SCK ; bit1=CS
debug("hdisp\n");
SSD_REGWB(0xac,0x7);//all pull high at start
SSD_REGWB(0xac,0x0);//send 0
SSD_REGWB(0xac,0x2);//send 0 and pull up SCK
SSD_REGWB(0xac,0x0);
SSD_REGWB(0xac,0x2);
SSD_REGWB(0xac,0x4);
SSD_REGWB(0xac,0x6);
SSD_REGWB(0xac,0x0);
SSD_REGWB(0xac,0x2);
SSD_REGWB(0xac,0x0);
SSD_REGWB(0xac,0x2);
SSD_REGWB(0xac,0x4);
SSD_REGWB(0xac,0x6);
SSD_REGWB(0xac,0x4);
SSD_REGWB(0xac,0x6);
SSD_REGWB(0xac,0x0);
SSD_REGWB(0xac,0x2);
SSD_REGWB(0xac,0x0);
SSD_REGWB(0xac,0x2);
SSD_REGWB(0xac,0x0);
SSD_REGWB(0xac,0x2);
SSD_REGWB(0xac,0x0);
SSD_REGWB(0xac,0x2);
SSD_REGWB(0xac,0x0);
SSD_REGWB(0xac,0x2);
SSD_REGWB(0xac,0x7);//all pull high at the end
debug("send gpio cmd\n");
//gpio cmd
SSD_REGWB(0xac,0x7);
SSD_REGWB(0xac,0x0);
SSD_REGWB(0xac,0x2);
SSD_REGWB(0xac,0x4);
SSD_REGWB(0xac,0x6);
SSD_REGWB(0xac,0x4);
SSD_REGWB(0xac,0x6);
SSD_REGWB(0xac,0x0);
SSD_REGWB(0xac,0x2);
SSD_REGWB(0xac,0x0);
SSD_REGWB(0xac,0x2);
SSD_REGWB(0xac,0x0);
SSD_REGWB(0xac,0x2);
SSD_REGWB(0xac,0x0);
SSD_REGWB(0xac,0x2);
SSD_REGWB(0xac,0x4);
SSD_REGWB(0xac,0x6);
SSD_REGWB(0xac,0x4);
SSD_REGWB(0xac,0x6);
SSD_REGWB(0xac,0x0);
SSD_REGWB(0xac,0x2);
SSD_REGWB(0xac,0x0);
SSD_REGWB(0xac,0x2);
SSD_REGWB(0xac,0x0);
SSD_REGWB(0xac,0x2);
SSD_REGWB(0xac,0x7);
//set contrast
SSD_REGWB(0xac,0x07);
SSD_REGWB(0xac,0x00);
SSD_REGWB(0xac,0x02);
SSD_REGWB(0xac,0x04);
SSD_REGWB(0xac,0x06);
SSD_REGWB(0xac,0x00);
SSD_REGWB(0xac,0x02);
SSD_REGWB(0xac,0x00);
SSD_REGWB(0xac,0x02);
SSD_REGWB(0xac,0x04);
SSD_REGWB(0xac,0x06);
SSD_REGWB(0xac,0x04);
SSD_REGWB(0xac,0x06);
SSD_REGWB(0xac,0x04);
SSD_REGWB(0xac,0x06);
SSD_REGWB(0xac,0x04);
SSD_REGWB(0xac,0x06);
SSD_REGWB(0xac,0x00);
SSD_REGWB(0xac,0x02);
SSD_REGWB(0xac,0x00);
SSD_REGWB(0xac,0x02);
SSD_REGWB(0xac,0x04);
SSD_REGWB(0xac,0x06);
SSD_REGWB(0xac,0x04);
SSD_REGWB(0xac,0x06);
SSD_REGWB(0xac,0x07);
//set brightness
SSD_REGWB(0xac,0x07);
SSD_REGWB(0xac,0x00);
SSD_REGWB(0xac,0x02);
SSD_REGWB(0xac,0x00);
SSD_REGWB(0xac,0x02);
SSD_REGWB(0xac,0x00);
SSD_REGWB(0xac,0x02);
SSD_REGWB(0xac,0x00);
SSD_REGWB(0xac,0x02);
SSD_REGWB(0xac,0x00);
SSD_REGWB(0xac,0x02);
SSD_REGWB(0xac,0x00);
SSD_REGWB(0xac,0x02);
SSD_REGWB(0xac,0x00);
SSD_REGWB(0xac,0x02);
SSD_REGWB(0xac,0x04);
SSD_REGWB(0xac,0x06);
SSD_REGWB(0xac,0x04);
SSD_REGWB(0xac,0x06);
SSD_REGWB(0xac,0x04);
SSD_REGWB(0xac,0x06);
SSD_REGWB(0xac,0x00);
SSD_REGWB(0xac,0x02);
SSD_REGWB(0xac,0x00);
SSD_REGWB(0xac,0x02);
SSD_REGWB(0xac,0x07);
//flip/* SSD_REGWB(0xac,0x07); SSD_REGWB(0xac,0x00);//0 SSD_REGWB(0xac,0x02); SSD_REGWB(0xac,0x04);//1 SSD_REGWB(0xac,0x06); SSD_REGWB(0xac,0x04);//1 SSD_REGWB(0xac,0x06); SSD_REGWB(0xac,0x00);//0 SSD_REGWB(0xac,0x02); SSD_REGWB(0xac,0x00);//0//D4 SSD_REGWB(0xac,0x02); SSD_REGWB(0xac,0x04);//1//D5 up down reverse SSD_REGWB(0xac,0x06); SSD_REGWB(0xac,0x04);//1//D5 right left reverse SSD_REGWB(0xac,0x06); SSD_REGWB(0xac,0x04);//1//on backlight SSD_REGWB(0xac,0x06); SSD_REGWB(0xac,0x04);//1//Normal SSD_REGWB(0xac,0x06); SSD_REGWB(0xac,0x00);//0 SSD_REGWB(0xac,0x02); SSD_REGWB(0xac,0x00);//0 SSD_REGWB(0xac,0x02); SSD_REGWB(0xac,0x00);//0 SSD_REGWB(0xac,0x02); SSD_REGWB(0xac,0x07); SSD_REGWB(REG_DV_SUBPIXEL_MODE, 0x29);// even:BGR 101+odd RBG: 001*/}void setContrast(int value){ int bitNum; //set contrast SSD_REGWB(0xac,0x07);//pull high all //set address SSD_REGWB(0xac,0x00);//send 0 SSD_REGWB(0xac,0x02);//and pull up SCK when 0 is ready SSD_REGWB(0xac,0x04);//send 1 SSD_REGWB(0xac,0x06); SSD_REGWB(0xac,0x00);//send 0 SSD_REGWB(0xac,0x02); SSD_REGWB(0xac,0x00);//send 0 SSD_REGWB(0xac,0x02); //set value if(value>0xF) { value=0xF; } if(value<0) { value=0; } for(bitNum=0;bitNum<4;bitNum++) { if(value&(0x1<<bitNum)) { SSD_REGWB(0xac,0x04);//send 1 SSD_REGWB(0xac,0x06); } else { SSD_REGWB(0xac,0x00);//send 0 SSD_REGWB(0xac,0x02); } } //speical settings SSD_REGWB(0xac,0x00);//send 0 SSD_REGWB(0xac,0x02); SSD_REGWB(0xac,0x00);//send 0 SSD_REGWB(0xac,0x02); SSD_REGWB(0xac,0x04);//send 1 SSD_REGWB(0xac,0x06); SSD_REGWB(0xac,0x04);//send 1 SSD_REGWB(0xac,0x06); SSD_REGWB(0xac,0x07);//pull high all}void setBrightness(int value){ int bitNum; //set brightness SSD_REGWB(0xac,0x07); //set address SSD_REGWB(0xac,0x00);//send 0 SSD_REGWB(0xac,0x02); SSD_REGWB(0xac,0x00);//send 0 SSD_REGWB(0xac,0x02); SSD_REGWB(0xac,0x00);//send 0 SSD_REGWB(0xac,0x02); SSD_REGWB(0xac,0x00);//send 0 SSD_REGWB(0xac,0x02); //don't care SSD_REGWB(0xac,0x00); SSD_REGWB(0xac,0x02); SSD_REGWB(0xac,0x00); SSD_REGWB(0xac,0x02); //set value if(value>0x3F) { value=0x3F; } if(value<0) { value=0; } for(bitNum=0;bitNum<6;bitNum++) { if(value&(0x1<<bitNum)) { SSD_REGWB(0xac,0x04);//send 1 SSD_REGWB(0xac,0x06); } else { SSD_REGWB(0xac,0x00);//send 0 SSD_REGWB(0xac,0x02); } } SSD_REGWB(0xac,0x07);}
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