📄 tianma.c

📁 ssd192X_LPC2210_V2.0 LPC2210的16位数据口控制SSD1926
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		SSD_REGWB( REG_GPIO_STATUS_CONTROL0,0x02);		SSD_REGWB( REG_GPIO_STATUS_CONTROL0,0x06);		SSD_REGWB( REG_GPIO_STATUS_CONTROL0,0x07);//display on		SSD_REGWB( REG_POWER_SAVE_CONFIG,0x00);//	printk("Initialize AU 3 Panel\n");#else//	printk("Initialize CASIO 2.7\" Panel\n");#endif	while(lcd_hw_init[i][0]!=REG_DEFINE_END)	{		SSD_REGWB(lcd_hw_init[i][0],lcd_hw_init[i][1]);		i++;	}/*	SSD_IOB(0x70)=0x44;	SSD_IOB(0x1a4)=0x00;	SSD_IOB(0x12)=0x15;	SSD_IOB(0x13)=0x07;	SSD_IOB(0x14)=0x13;	SSD_IOB(0x16)=0x04;	SSD_IOB(0x18)=240;	SSD_IOB(0x1c)=239;	SSD_IOB(0x1e)=0;	SSD_IOB(0x30)=1;	SSD_IOB(0x22)=1;	SSD_IOB(0x78)=0x50;	SSD_IOB(0x74)=0x0;	SSD_IOB(0x71)=0x40;*/	#if 0 //ndef__AU030//printk("send hdips\n");	//hdisp	printk("hdisp\n");	SSD_REGWB(0xac,0x7);	SSD_REGWB(0xac,0x0);	SSD_REGWB(0xac,0x2);	SSD_REGWB(0xac,0x0);	SSD_REGWB(0xac,0x2);	SSD_REGWB(0xac,0x4);	SSD_REGWB(0xac,0x6);	SSD_REGWB(0xac,0x0);	SSD_REGWB(0xac,0x2);	SSD_REGWB(0xac,0x0);	SSD_REGWB(0xac,0x2);	SSD_REGWB(0xac,0x4);	SSD_REGWB(0xac,0x6);	SSD_REGWB(0xac,0x4);	SSD_REGWB(0xac,0x6);	SSD_REGWB(0xac,0x0);	SSD_REGWB(0xac,0x2);	SSD_REGWB(0xac,0x0);	SSD_REGWB(0xac,0x2);	SSD_REGWB(0xac,0x0);	SSD_REGWB(0xac,0x2);	SSD_REGWB(0xac,0x0);	SSD_REGWB(0xac,0x2);	SSD_REGWB(0xac,0x0);	SSD_REGWB(0xac,0x2);	SSD_REGWB(0xac,0x7);//printk("send gpio cmd\n");	//gpio cmd	SSD_REGWB(0xac,0x7);	SSD_REGWB(0xac,0x0);	SSD_REGWB(0xac,0x2);	SSD_REGWB(0xac,0x4);	SSD_REGWB(0xac,0x6);	SSD_REGWB(0xac,0x4);	SSD_REGWB(0xac,0x6);	SSD_REGWB(0xac,0x0);	SSD_REGWB(0xac,0x2);	SSD_REGWB(0xac,0x0);	SSD_REGWB(0xac,0x2);	SSD_REGWB(0xac,0x4);	SSD_REGWB(0xac,0x6);	SSD_REGWB(0xac,0x4);	SSD_REGWB(0xac,0x6);	SSD_REGWB(0xac,0x4);	SSD_REGWB(0xac,0x6);	SSD_REGWB(0xac,0x4);	SSD_REGWB(0xac,0x6);	SSD_REGWB(0xac,0x0);	SSD_REGWB(0xac,0x2);	SSD_REGWB(0xac,0x0);	SSD_REGWB(0xac,0x2);	SSD_REGWB(0xac,0x0);	SSD_REGWB(0xac,0x2);	SSD_REGWB(0xac,0x7);	//set contrast	SSD_REGWB(0xac,0x07);//pull high all	//set address	SSD_REGWB(0xac,0x00);//send 0	SSD_REGWB(0xac,0x02);//and pull up SCK when 0 is ready	SSD_REGWB(0xac,0x04);//send 1	SSD_REGWB(0xac,0x06);	SSD_REGWB(0xac,0x00);//send 0	SSD_REGWB(0xac,0x02);	SSD_REGWB(0xac,0x00);//send 0	SSD_REGWB(0xac,0x02);	//set value	SSD_REGWB(0xac,0x04);//send 1	SSD_REGWB(0xac,0x06);	SSD_REGWB(0xac,0x04);//send 1	SSD_REGWB(0xac,0x06);	SSD_REGWB(0xac,0x04);//send 1	SSD_REGWB(0xac,0x06);	SSD_REGWB(0xac,0x04);//send 1	SSD_REGWB(0xac,0x06);		//speical settings	SSD_REGWB(0xac,0x00);//send 0	SSD_REGWB(0xac,0x02);	SSD_REGWB(0xac,0x00);//send 0	SSD_REGWB(0xac,0x02); 	SSD_REGWB(0xac,0x04);//send 1	SSD_REGWB(0xac,0x06);	SSD_REGWB(0xac,0x04);//send 1	SSD_REGWB(0xac,0x06); 	SSD_REGWB(0xac,0x07);//pull high all		//set brightness	SSD_REGWB(0xac,0x07);	SSD_REGWB(0xac,0x00);	SSD_REGWB(0xac,0x02);	SSD_REGWB(0xac,0x00);	SSD_REGWB(0xac,0x02);	SSD_REGWB(0xac,0x00);	SSD_REGWB(0xac,0x02);	SSD_REGWB(0xac,0x00);	SSD_REGWB(0xac,0x02);	SSD_REGWB(0xac,0x00);	SSD_REGWB(0xac,0x02);	SSD_REGWB(0xac,0x00);	SSD_REGWB(0xac,0x02);	SSD_REGWB(0xac,0x00);	SSD_REGWB(0xac,0x02);	SSD_REGWB(0xac,0x04);	SSD_REGWB(0xac,0x06);	SSD_REGWB(0xac,0x04);	SSD_REGWB(0xac,0x06);	SSD_REGWB(0xac,0x04);	SSD_REGWB(0xac,0x06);	SSD_REGWB(0xac,0x00);	SSD_REGWB(0xac,0x02);	SSD_REGWB(0xac,0x00);	SSD_REGWB(0xac,0x02);	SSD_REGWB(0xac,0x07);	#endif		}#if 0void setContrast(int value){	int bitNum;	//set contrast	SSD_REGWB(0xac,0x07);//pull high all	//set address	SSD_REGWB(0xac,0x00);//send 0	SSD_REGWB(0xac,0x02);//and pull up SCK when 0 is ready	SSD_REGWB(0xac,0x04);//send 1	SSD_REGWB(0xac,0x06);	SSD_REGWB(0xac,0x00);//send 0	SSD_REGWB(0xac,0x02);	SSD_REGWB(0xac,0x00);//send 0	SSD_REGWB(0xac,0x02);			//set value	if(value>0xF)	{		value=0xF;	}	if(value<0)	{		value=0;	}	for(bitNum=0;bitNum<4;bitNum++)	{		if(value&(0x1<<bitNum))		{			SSD_REGWB(0xac,0x04);//send 1			SSD_REGWB(0xac,0x06);		}		else		{			SSD_REGWB(0xac,0x00);//send 0			SSD_REGWB(0xac,0x02);		}	}	//speical settings	SSD_REGWB(0xac,0x00);//send 0	SSD_REGWB(0xac,0x02);	SSD_REGWB(0xac,0x00);//send 0	SSD_REGWB(0xac,0x02); 	SSD_REGWB(0xac,0x04);//send 1	SSD_REGWB(0xac,0x06);	SSD_REGWB(0xac,0x04);//send 1	SSD_REGWB(0xac,0x06); 	SSD_REGWB(0xac,0x07);//pull high all}void setBrightness(int value){	int bitNum;	//set brightness	SSD_REGWB(0xac,0x07);	//set address	SSD_REGWB(0xac,0x00);//send 0	SSD_REGWB(0xac,0x02);	SSD_REGWB(0xac,0x00);//send 0	SSD_REGWB(0xac,0x02);	SSD_REGWB(0xac,0x00);//send 0	SSD_REGWB(0xac,0x02);	SSD_REGWB(0xac,0x00);//send 0	SSD_REGWB(0xac,0x02);	//don't care	SSD_REGWB(0xac,0x00);	SSD_REGWB(0xac,0x02);	SSD_REGWB(0xac,0x00);	SSD_REGWB(0xac,0x02);	//set value	if(value>0x3F)	{		value=0x3F;	}	if(value<0)	{		value=0;	}	for(bitNum=0;bitNum<6;bitNum++)	{		if(value&(0x1<<bitNum))		{			SSD_REGWB(0xac,0x04);//send 1			SSD_REGWB(0xac,0x06);		}		else		{			SSD_REGWB(0xac,0x00);//send 0			SSD_REGWB(0xac,0x02);		}	}	SSD_REGWB(0xac,0x07);}#elsevoid setContrast(int value)
{
	int bitNum;
	
	debug("AUO panel SET CONTRAST ***************\n");
	//set contrast
	SSD_REGWB(0xac,0x07);//pull high all

	//set address
	SSD_REGWB(0xac,0x00);//send 0
	SSD_REGWB(0xac,0x04);//and pull up SCK when 0 is ready

	SSD_REGWB(0xac,0x00);//send 0
	SSD_REGWB(0xac,0x04);

	SSD_REGWB(0xac,0x00);//send 0
	SSD_REGWB(0xac,0x04);

	SSD_REGWB(0xac,0x00);//send 0
	SSD_REGWB(0xac,0x04);

	SSD_REGWB(0xac,0x02);//send 1
	SSD_REGWB(0xac,0x06);	

	SSD_REGWB(0xac,0x02);//send 1
	SSD_REGWB(0xac,0x06);	

	SSD_REGWB(0xac,0x00);//send 0
	SSD_REGWB(0xac,0x04);
	
	SSD_REGWB(0xac,0x02);//send 1
	SSD_REGWB(0xac,0x06);	
			
	//set value

	if(value>0xFF)
	{
		value=0xF;
	}
	if(value<0)
	{
		value=0;
	}

	for(bitNum=7;bitNum>=0;bitNum--)
	{
		if(value&(0x1<<bitNum))
		{
			SSD_REGWB(0xac,0x02);//send 1
			SSD_REGWB(0xac,0x06);
			debug("AUO panel serial link: 1 ***************\n");
		}
		else
		{
			SSD_REGWB(0xac,0x00);//send 0
			SSD_REGWB(0xac,0x04);
			debug("AUO panel serial link: 0***************\n");
		}
	}
	
	SSD_REGWB(0xac,0x07);//pull high all

}

void setBrightness(int value)
{
	int bitNum;
	//set brightness
	
	debug("AUO panel SET BRIGHTNESS ***************\n");
	
	SSD_REGWB(REG_GPIO_STATUS_CONTROL0,0x07);//pull high all

	//set address
	SSD_REGWB(REG_GPIO_STATUS_CONTROL0,0x00);//send 0
	SSD_REGWB(REG_GPIO_STATUS_CONTROL0,0x04);//and pull up SCK when 0 is ready

	SSD_REGWB(REG_GPIO_STATUS_CONTROL0,0x00);//send 0
	SSD_REGWB(REG_GPIO_STATUS_CONTROL0,0x04);

	SSD_REGWB(REG_GPIO_STATUS_CONTROL0,0x00);//send 0
	SSD_REGWB(REG_GPIO_STATUS_CONTROL0,0x04);

	SSD_REGWB(REG_GPIO_STATUS_CONTROL0,0x00);//send 0
	SSD_REGWB(REG_GPIO_STATUS_CONTROL0,0x04);

	SSD_REGWB(REG_GPIO_STATUS_CONTROL0,0x00);//send 0
	SSD_REGWB(REG_GPIO_STATUS_CONTROL0,0x04);
	
	SSD_REGWB(REG_GPIO_STATUS_CONTROL0,0x00);//send 0
	SSD_REGWB(REG_GPIO_STATUS_CONTROL0,0x04);

	SSD_REGWB(REG_GPIO_STATUS_CONTROL0,0x02);//send 1
	SSD_REGWB(REG_GPIO_STATUS_CONTROL0,0x06);	

	SSD_REGWB(REG_GPIO_STATUS_CONTROL0,0x02);//send 1
	SSD_REGWB(REG_GPIO_STATUS_CONTROL0,0x06);	
			
	//set value

	if(value>0xFF)
	{
		value=0xF;
	}
	if(value<0)
	{
		value=0;
	}

	for(bitNum=7;bitNum>=0;bitNum--)
	{
		if(value&(0x1<<bitNum))
		{
			SSD_REGWB(REG_GPIO_STATUS_CONTROL0,0x02);//send 1
			SSD_REGWB(REG_GPIO_STATUS_CONTROL0,0x06);
			debug("AUO panel serial link: 1 ***************\n");
		}
		else
		{
			SSD_REGWB(REG_GPIO_STATUS_CONTROL0,0x00);//send 0
			SSD_REGWB(REG_GPIO_STATUS_CONTROL0,0x04);
			debug("AUO panel serial link: 0***************\n");
		}
	}
	
	SSD_REGWB(0xac,0x07);//pull high all
}#endif
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