📄 td035.c
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#include "ssd192X.h"int LCD_WIDTH=320;int LCD_HEIGHT=240;int WIDE_TFT=0;void lcd_hw_init(void){ int i=0; INT32 lcd_hw_init[][2]= { {REG_FPFRAME_START_OFFSET0 ,0x00}, {REG_FPFRAME_START_OFFSET1 ,0x00}, {REG_FPFRAME_STOP_OFFSET0 ,0x00}, {REG_FPFRAME_STOP_OFFSET1 ,0x00}, {REG_PCLK_FREQ_RATIO_0 ,0xff}, {REG_PCLK_FREQ_RATIO_1 ,0xff}, {REG_PCLK_FREQ_RATIO_2 ,0x01}, {REG_PANEL_TYPE ,0x61}, {REG_MOD_RATE ,0x00}, {REG_HORIZ_TOTAL_0 ,0x36}, {REG_HORIZ_TOTAL_1 ,0x07}, {REG_HDP ,0x27}, {REG_HDP_START_POS0 ,0x48}, {REG_HDP_START_POS1 ,0x00}, {REG_VERT_TOTAL0 ,0x07}, {REG_VERT_TOTAL1 ,0x01}, {REG_VDP0 ,0xef}, {REG_VDP1 ,0x00}, {REG_VDP_START_POS0 ,0x0c}, {REG_VDP_START_POS1 ,0x00}, {REG_HSYNC_PULSE_WIDTH ,0x25}, {REG_HSYNC_PULSE_START_POS0 ,0x00}, {REG_HSYNC_PULSE_START_POS1 ,0x00}, {REG_VSYNC_PULSE_WIDTH ,0x07}, {REG_VSYNC_PULSE_START_POS0 ,0x00}, {REG_VSYNC_PULSE_START_POS1 ,0x00}, {REG_GPIO_STATUS_CONTROL1 ,0x80}, // ,0x00}, {REG_HRTFT_SPECIAL_OUTPUT ,0x01}, {REG_DISPLAY_MODE ,0x44}, {REG_SPECIAL_EFFECTS ,0xc4}, {REG_DEFINE_END ,0x00} }; debug("Initialize TD035\n"); while(lcd_hw_init[i][0]!=REG_DEFINE_END) { SSD_REGWB(lcd_hw_init[i][0],lcd_hw_init[i][1]); i++; }#if 1//set gpio to output SSD_REGWB( REG_GPIO_CONFIG0,0x07);// GPIO0 = CS//GPIO1 = SDA// GPIO2 = SCL#endif//software reset SSD_REGWB(0xac,0x7); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x7);//blank period SSD_REGWB(0xac,0x7); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); // SSD_REGWB(0xac,0x4); // SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x7);//display mode SSD_REGWB(0xac,0x7); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x7);//VCOM setting SSD_REGWB(0xac,0x7); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x7);#if 0//ASW timing control SSD_REGWB(0xac,0x7); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x7);#endif//sleep out SSD_REGWB(0xac,0x7); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x7);//display on SSD_REGWB(0xac,0x7); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x7);/*//display inversion on SSD_REGWB(0xac,0x7); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x0); SSD_REGWB(0xac,0x2); SSD_REGWB(0xac,0x4); SSD_REGWB(0xac,0x6); SSD_REGWB(0xac,0x7);*/}⌨️ 快捷键说明
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