alarm_block.v

基于verilog的时钟定时器的硬件实现

module ALARM_BLOCK(CLK, HRS, MINS, ALARM, HRS_OUT, MINS_OUT, AM_PM, RESET);
input CLK, HRS, MINS, ALARM, RESET;
output HRS_OUT, MINS_OUT, AM_PM;
wire CLK, HRS, MINS, ALARM, RESET;
wire AM_PM;
wire [3:0] HRS_OUT;
wire [5:0] MINS_OUT;

wire HRS_OUT_IN, MINS_OUT_IN;

ALARM_STATE_MACHINE
alarm_machine(CLK, HRS, MINS, ALARM, HRS_OUT_IN, MINS_OUT_IN);
ALARM_COUNTER
alarm_counter(CLK, HRS_OUT_IN, MINS_OUT_IN, ALARM, HRS_OUT, MINS_OUT, AM_PM, RESET);

endmodule