testbench.v

基于verilog的时钟定时器的硬件实现

`timescale 10ns/1ns
module testbench;
reg RESET, ALARM,CLK,HRS,MINS,SET_TIME,TOGGLE_SWITCH;
wire [9:0] OUTBUS;
wire AM_PM_SHOW,SPEAKER_OUT;

TOP top(CLK,ALARM,HRS,MINS,SET_TIME,RESET,TOGGLE_SWITCH,AM_PM_SHOW,OUTBUS,SPEAKER_OUT);


initial 
	fork
	   RESET=0;
		ALARM=0;
		CLK=1;
		HRS=0;
		MINS=0;
		SET_TIME=0;
		TOGGLE_SWITCH=0;
		#11 RESET=1;
		#13 RESET=0;
		#74 begin
			SET_TIME=1;
			MINS=1;
		end
		#82 begin 
			HRS=1;
			MINS=0;
		end
		#91 begin;
			MINS=0;
			HRS=0;
		end
		#91.2  SET_TIME=0;
		#102 begin
			ALARM=1;
			MINS=1;
		end
		#123 begin 
			MINS=0;
			HRS=1;
		end
		#137    HRS=0;
		#137.2	ALARM=0;
		#201 TOGGLE_SWITCH=1;
		#42002 TOGGLE_SWITCH=0;
		//#24000 RESET=1;
		//#24010 RESET=0;
		#50000 $finish;
	join
	
always #0.5 CLK=~CLK;

endmodule