comparator.v

基于verilog的时钟定时器的硬件实现

module COMPARATOR(ALARM_HRS, ALARM_MIN, ALARM_AM_PM, TIME_HRS, TIME_MIN, TIME_AM_PM, MATCH);
input ALARM_HRS, ALARM_MIN, ALARM_AM_PM, TIME_HRS, TIME_MIN, TIME_AM_PM;
output MATCH;
wire [3:0] ALARM_HRS, TIME_HRS;
wire [5:0] ALARM_MIN, TIME_MIN;
wire ALARM_AM_PM, TIME_AM_PM;
reg MATCH;

always@(*)
  begin
     if({ALARM_HRS, ALARM_MIN, ALARM_AM_PM}=={TIME_HRS, TIME_MIN, TIME_AM_PM})
         MATCH= 1;
     else
         MATCH= 0;
  end

endmodule