time_block.v

基于verilog的时钟定时器的硬件实现

module TIME_BLOCK(CLK, HRS, MINS,SET_TIME, HRS_OUT, MINS_OUT, AM_PM, RESET);
input CLK, HRS, MINS, SET_TIME, RESET;
output HRS_OUT, MINS_OUT, AM_PM;
wire CLK, HRS, MINS, SET_TIME, AM_PM, RESET;
wire [3:0] HRS_OUT;
wire [5:0] MINS_OUT;
wire HRS_OUT_IN, MINS_OUT_IN, SECS_OUT_IN;

TIME_STATE_MACHINE
time_machine(CLK, HRS, MINS, SET_TIME, HRS_OUT_IN, MINS_OUT_IN, SECS_OUT_IN);

TIME_COUNTER
time_counter(CLK, HRS_OUT_IN, MINS_OUT_IN, SECS_OUT_IN, HRS_OUT, MINS_OUT, AM_PM, RESET);

endmodule