top.v

基于verilog的时钟定时器的硬件实现

module TOP(CLK, ALARM, HRS, MINS, SET_TIME,RESET, 
           TOGGLE_SWITCH, AM_PM_SHOW,
           SHOW_HRS, SHOW_MINS, SPEAKER);
input CLK, ALARM, HRS, MINS, SET_TIME, RESET,TOGGLE_SWITCH;
output AM_PM_SHOW, SHOW_HRS, SHOW_MINS, SPEAKER;
wire CLK, ALARM, HRS, MINS, SET_TIME, RESET, TOGGLE_SWITCH;
wire AM_PM_SHOW, SPEAKER;
wire [13:0] SHOW_HRS,SHOW_MINS;

wire [9:0] BUS;
wire [3:0] ALARM_HRS_OUT;
wire [5:0] ALARM_MINS_OUT;
wire ALARM_AM_PM_OUT;

wire [3:0] TIME_HRS_OUT;
wire [5:0] TIME_MINS_OUT;
wire TIME_AM_PM_OUT;

wire COMPARATOR_OUT;

ALARM_BLOCK
alarm_block(CLK, HRS, MINS, ALARM, ALARM_HRS_OUT, ALARM_MINS_OUT, ALARM_AM_PM_OUT, RESET);

TIME_BLOCK
time_block(CLK, HRS, MINS, SET_TIME, TIME_HRS_OUT, TIME_MINS_OUT, TIME_AM_PM_OUT, RESET);

Mux
mux(ALARM, ALARM_HRS_OUT, ALARM_MINS_OUT, ALARM_AM_PM_OUT,
    TIME_HRS_OUT, TIME_MINS_OUT, TIME_AM_PM_OUT,
    AM_PM_SHOW, BUS);
    
COMPARATOR
comparator(ALARM_HRS_OUT, ALARM_MINS_OUT, ALARM_AM_PM_OUT,
           TIME_HRS_OUT, TIME_MINS_OUT, TIME_AM_PM_OUT,
           COMPARATOR_OUT);
           
ALARM_SM_2
alarm_sm_2(CLK, COMPARATOR_OUT, TOGGLE_SWITCH, SPEAKER);

CONVERTOR_CKT
convertor_ckt(BUS, SHOW_HRS, SHOW_MINS);

endmodule