convertor_ckt.v

基于verilog的时钟定时器的硬件实现

module CONVERTOR_CKT(INBUS, HRS_SHOW, MINS_SHOW);
input INBUS;
output HRS_SHOW, MINS_SHOW;
wire [9:0] INBUS;
reg [13:0] HRS_SHOW, MINS_SHOW;

always@(INBUS[9:6])
  begin 
   case(INBUS[9:6])
        4'b0000:	  HRS_SHOW = 14'b1111111_1000000;
	4'b0001:	  HRS_SHOW = 14'b1111111_1111001;
	4'b0010:	  HRS_SHOW = 14'b1111111_0100100;
	4'b0011:	  HRS_SHOW = 14'b1111111_0110000;
	4'b0100:	  HRS_SHOW = 14'b1111111_0011001;
	4'b0101:	  HRS_SHOW = 14'b1111111_0010010;
	4'b0110:	  HRS_SHOW = 14'b1111111_0000011;
	4'b0111:	  HRS_SHOW = 14'b1111111_1111000;
	4'b1000:	  HRS_SHOW = 14'b1111111_0000000;
	4'b1001:	  HRS_SHOW = 14'b1111111_0011000;
	4'b1010:	  HRS_SHOW = 14'b1111001_1000000;
	4'b1011:	  HRS_SHOW = 14'b1111001_1111001; 
	default:   HRS_SHOW = 14'b1001111_1001111;
    endcase
  end
  
always@(INBUS[5:0])
   begin
      case(INBUS[5:0])
        6'd0:    MINS_SHOW = 14'b1111111_1000000;
        6'd1:    MINS_SHOW = 14'b1111111_1111001;
        6'd2:    MINS_SHOW = 14'b1111111_0100100;
        6'd3:    MINS_SHOW = 14'b1111111_0110000;
        6'd4:    MINS_SHOW = 14'b1111111_0011001;
        6'd5:    MINS_SHOW = 14'b1111111_0010010;
        6'd6:    MINS_SHOW = 14'b1111111_0000011;
        6'd7:    MINS_SHOW = 14'b1111111_1111000;
        6'd8:    MINS_SHOW = 14'b1111111_0000000;
        6'd9:    MINS_SHOW = 14'b1111111_0011000;
        6'd10:   MINS_SHOW = 14'b1111001_1000000;
        6'd11:   MINS_SHOW = 14'b1111001_1111001;
        6'd12:   MINS_SHOW = 14'b1111001_0100100;
        6'd13:   MINS_SHOW = 14'b1111001_0110000;
        6'd14:   MINS_SHOW = 14'b1111001_0011001;
        6'd15:   MINS_SHOW = 14'b1111001_0010010;
        6'd16:   MINS_SHOW = 14'b1111001_0000011;
        6'd17:   MINS_SHOW = 14'b1111001_1111000;
        6'd18:   MINS_SHOW = 14'b1111001_0000000;
        6'd19:   MINS_SHOW = 14'b1111001_0011000;
        6'd20:   MINS_SHOW = 14'b0100100_1000000;
        6'd21:   MINS_SHOW = 14'b0100100_1111001;
        6'd22:   MINS_SHOW = 14'b0100100_0100100;
        6'd23:   MINS_SHOW = 14'b0100100_0110000;
        6'd24:   MINS_SHOW = 14'b0100100_0011001;
        6'd25:   MINS_SHOW = 14'b0100100_0010010;
        6'd26:   MINS_SHOW = 14'b0100100_0000011;
        6'd27:   MINS_SHOW = 14'b0100100_1111000;
        6'd28:   MINS_SHOW = 14'b0100100_0000000;
        6'd29:   MINS_SHOW = 14'b0100100_0011000;
        6'd30:   MINS_SHOW = 14'b0110000_1000000;
        6'd31:   MINS_SHOW = 14'b0110000_1111001;
        6'd32:   MINS_SHOW = 14'b0110000_0100100;
        6'd33:   MINS_SHOW = 14'b0110000_0110000;
        6'd34:   MINS_SHOW = 14'b0110000_0011001;
        6'd35:   MINS_SHOW = 14'b0110000_0010010;
        6'd36:   MINS_SHOW = 14'b0110000_0000011;
        6'd37:   MINS_SHOW = 14'b0110000_1111000;
        6'd38:   MINS_SHOW = 14'b0110000_0000000;
        6'd39:   MINS_SHOW = 14'b0110000_0011000;
        6'd40:   MINS_SHOW = 14'b0011001_1000000;
        6'd41:   MINS_SHOW = 14'b0011001_1111001;
        6'd42:   MINS_SHOW = 14'b0011001_0100100;
        6'd43:   MINS_SHOW = 14'b0011001_0110000;
        6'd44:   MINS_SHOW = 14'b0011001_0011001;
        6'd45:   MINS_SHOW = 14'b0011001_0010010;
        6'd46:   MINS_SHOW = 14'b0011001_0000011;
        6'd47:   MINS_SHOW = 14'b0011001_1111000;
        6'd48:   MINS_SHOW = 14'b0011001_0000000;
        6'd49:   MINS_SHOW = 14'b0011001_0011000;
        6'd50:   MINS_SHOW = 14'b0010010_1000000;
        6'd51:   MINS_SHOW = 14'b0010010_1111001;
        6'd52:   MINS_SHOW = 14'b0010010_0100100;
        6'd53:   MINS_SHOW = 14'b0010010_0110000;
        6'd54:   MINS_SHOW = 14'b0010010_0011001;
        6'd55:   MINS_SHOW = 14'b0010010_0010010;
        6'd56:   MINS_SHOW = 14'b0010010_0000011;
        6'd57:   MINS_SHOW = 14'b0010010_1111000;
        6'd58:   MINS_SHOW = 14'b0010010_0000000;
        6'd59:   MINS_SHOW = 14'b0010010_0011000;	
        default:  MINS_SHOW = 14'b1001111_1001111;
      endcase
   end
   
endmodule