alarm_sm_2.v

基于verilog的时钟定时器的硬件实现

module ALARM_SM_2(CLK, COMPARE_IN, TOGGLE_ON, RING);
input CLK, COMPARE_IN, TOGGLE_ON;
output RING;
wire CLK, COMPARE_IN, TOGGLE_ON;
reg RING;

reg STATE, NEXTSTATE;
parameter IDLE= 1'b0, ACTIVE= 1'b1;

   
 always@(posedge CLK)
   begin
      case(STATE)
         IDLE:
           begin
              RING<= 0;
              if(TOGGLE_ON==1 & COMPARE_IN== 1)
                  NEXTSTATE<= ACTIVE;
              else
                  NEXTSTATE<= STATE;
           end
         ACTIVE:
           begin   
              RING<= 1;
              if(TOGGLE_ON==1)  
                  NEXTSTATE<= STATE;
              else
                  NEXTSTATE<= IDLE;
           end
        default:
          begin
              RING<= 0;
              NEXTSTATE<= IDLE;
          end
     endcase
   end
always @(posedge CLK)
     STATE<= NEXTSTATE;

endmodule