psocgpioint.h

Cypress公司开发的2.4G无线键盘鼠标及其Bridge源代码

/******************************************************************************
*  Generated by PSoC Designer ver 4.4  b1884 : 14 Jan, 2007
******************************************************************************/
#include <m8c.h>
// nLED1 address and mask defines
#pragma	ioport	nLED1_Data_ADDR:	0x0
BYTE			nLED1_Data_ADDR;
#pragma	ioport	nLED1_DriveMode_0_ADDR:	0x100
BYTE			nLED1_DriveMode_0_ADDR;
#pragma	ioport	nLED1_DriveMode_1_ADDR:	0x101
BYTE			nLED1_DriveMode_1_ADDR;
#pragma	ioport	nLED1_DriveMode_2_ADDR:	0x3
BYTE			nLED1_DriveMode_2_ADDR;
#pragma	ioport	nLED1_GlobalSelect_ADDR:	0x2
BYTE			nLED1_GlobalSelect_ADDR;
#pragma	ioport	nLED1_IntCtrl_0_ADDR:	0x102
BYTE			nLED1_IntCtrl_0_ADDR;
#pragma	ioport	nLED1_IntCtrl_1_ADDR:	0x103
BYTE			nLED1_IntCtrl_1_ADDR;
#pragma	ioport	nLED1_IntEn_ADDR:	0x1
BYTE			nLED1_IntEn_ADDR;
#define nLED1_MASK 0x20
#pragma	ioport	nLED1_MUXBusCtrl_ADDR:	0x1d8
BYTE			nLED1_MUXBusCtrl_ADDR;
// nLED2 address and mask defines
#pragma	ioport	nLED2_Data_ADDR:	0x0
BYTE			nLED2_Data_ADDR;
#pragma	ioport	nLED2_DriveMode_0_ADDR:	0x100
BYTE			nLED2_DriveMode_0_ADDR;
#pragma	ioport	nLED2_DriveMode_1_ADDR:	0x101
BYTE			nLED2_DriveMode_1_ADDR;
#pragma	ioport	nLED2_DriveMode_2_ADDR:	0x3
BYTE			nLED2_DriveMode_2_ADDR;
#pragma	ioport	nLED2_GlobalSelect_ADDR:	0x2
BYTE			nLED2_GlobalSelect_ADDR;
#pragma	ioport	nLED2_IntCtrl_0_ADDR:	0x102
BYTE			nLED2_IntCtrl_0_ADDR;
#pragma	ioport	nLED2_IntCtrl_1_ADDR:	0x103
BYTE			nLED2_IntCtrl_1_ADDR;
#pragma	ioport	nLED2_IntEn_ADDR:	0x1
BYTE			nLED2_IntEn_ADDR;
#define nLED2_MASK 0x80
#pragma	ioport	nLED2_MUXBusCtrl_ADDR:	0x1d8
BYTE			nLED2_MUXBusCtrl_ADDR;
// LP_nSS address and mask defines
#pragma	ioport	LP_nSS_Data_ADDR:	0x4
BYTE			LP_nSS_Data_ADDR;
#pragma	ioport	LP_nSS_DriveMode_0_ADDR:	0x104
BYTE			LP_nSS_DriveMode_0_ADDR;
#pragma	ioport	LP_nSS_DriveMode_1_ADDR:	0x105
BYTE			LP_nSS_DriveMode_1_ADDR;
#pragma	ioport	LP_nSS_DriveMode_2_ADDR:	0x7
BYTE			LP_nSS_DriveMode_2_ADDR;
#pragma	ioport	LP_nSS_GlobalSelect_ADDR:	0x6
BYTE			LP_nSS_GlobalSelect_ADDR;
#pragma	ioport	LP_nSS_IntCtrl_0_ADDR:	0x106
BYTE			LP_nSS_IntCtrl_0_ADDR;
#pragma	ioport	LP_nSS_IntCtrl_1_ADDR:	0x107
BYTE			LP_nSS_IntCtrl_1_ADDR;
#pragma	ioport	LP_nSS_IntEn_ADDR:	0x5
BYTE			LP_nSS_IntEn_ADDR;
#define LP_nSS_MASK 0x4
#pragma	ioport	LP_nSS_MUXBusCtrl_ADDR:	0x1d9
BYTE			LP_nSS_MUXBusCtrl_ADDR;
// LP_IRQ address and mask defines
#pragma	ioport	LP_IRQ_Data_ADDR:	0x4
BYTE			LP_IRQ_Data_ADDR;
#pragma	ioport	LP_IRQ_DriveMode_0_ADDR:	0x104
BYTE			LP_IRQ_DriveMode_0_ADDR;
#pragma	ioport	LP_IRQ_DriveMode_1_ADDR:	0x105
BYTE			LP_IRQ_DriveMode_1_ADDR;
#pragma	ioport	LP_IRQ_DriveMode_2_ADDR:	0x7
BYTE			LP_IRQ_DriveMode_2_ADDR;
#pragma	ioport	LP_IRQ_GlobalSelect_ADDR:	0x6
BYTE			LP_IRQ_GlobalSelect_ADDR;
#pragma	ioport	LP_IRQ_IntCtrl_0_ADDR:	0x106
BYTE			LP_IRQ_IntCtrl_0_ADDR;
#pragma	ioport	LP_IRQ_IntCtrl_1_ADDR:	0x107
BYTE			LP_IRQ_IntCtrl_1_ADDR;
#pragma	ioport	LP_IRQ_IntEn_ADDR:	0x5
BYTE			LP_IRQ_IntEn_ADDR;
#define LP_IRQ_MASK 0x8
#pragma	ioport	LP_IRQ_MUXBusCtrl_ADDR:	0x1d9
BYTE			LP_IRQ_MUXBusCtrl_ADDR;
// SCK address and mask defines
#pragma	ioport	SCK_Data_ADDR:	0x4
BYTE			SCK_Data_ADDR;
#pragma	ioport	SCK_DriveMode_0_ADDR:	0x104
BYTE			SCK_DriveMode_0_ADDR;
#pragma	ioport	SCK_DriveMode_1_ADDR:	0x105
BYTE			SCK_DriveMode_1_ADDR;
#pragma	ioport	SCK_DriveMode_2_ADDR:	0x7
BYTE			SCK_DriveMode_2_ADDR;
#pragma	ioport	SCK_GlobalSelect_ADDR:	0x6
BYTE			SCK_GlobalSelect_ADDR;
#pragma	ioport	SCK_IntCtrl_0_ADDR:	0x106
BYTE			SCK_IntCtrl_0_ADDR;
#pragma	ioport	SCK_IntCtrl_1_ADDR:	0x107
BYTE			SCK_IntCtrl_1_ADDR;
#pragma	ioport	SCK_IntEn_ADDR:	0x5
BYTE			SCK_IntEn_ADDR;
#define SCK_MASK 0x10
#pragma	ioport	SCK_MUXBusCtrl_ADDR:	0x1d9
BYTE			SCK_MUXBusCtrl_ADDR;
// MISO address and mask defines
#pragma	ioport	MISO_Data_ADDR:	0x4
BYTE			MISO_Data_ADDR;
#pragma	ioport	MISO_DriveMode_0_ADDR:	0x104
BYTE			MISO_DriveMode_0_ADDR;
#pragma	ioport	MISO_DriveMode_1_ADDR:	0x105
BYTE			MISO_DriveMode_1_ADDR;
#pragma	ioport	MISO_DriveMode_2_ADDR:	0x7
BYTE			MISO_DriveMode_2_ADDR;
#pragma	ioport	MISO_GlobalSelect_ADDR:	0x6
BYTE			MISO_GlobalSelect_ADDR;
#pragma	ioport	MISO_IntCtrl_0_ADDR:	0x106
BYTE			MISO_IntCtrl_0_ADDR;
#pragma	ioport	MISO_IntCtrl_1_ADDR:	0x107
BYTE			MISO_IntCtrl_1_ADDR;
#pragma	ioport	MISO_IntEn_ADDR:	0x5
BYTE			MISO_IntEn_ADDR;
#define MISO_MASK 0x20
#pragma	ioport	MISO_MUXBusCtrl_ADDR:	0x1d9
BYTE			MISO_MUXBusCtrl_ADDR;
// MOSI address and mask defines
#pragma	ioport	MOSI_Data_ADDR:	0x4
BYTE			MOSI_Data_ADDR;
#pragma	ioport	MOSI_DriveMode_0_ADDR:	0x104
BYTE			MOSI_DriveMode_0_ADDR;
#pragma	ioport	MOSI_DriveMode_1_ADDR:	0x105
BYTE			MOSI_DriveMode_1_ADDR;
#pragma	ioport	MOSI_DriveMode_2_ADDR:	0x7
BYTE			MOSI_DriveMode_2_ADDR;
#pragma	ioport	MOSI_GlobalSelect_ADDR:	0x6
BYTE			MOSI_GlobalSelect_ADDR;
#pragma	ioport	MOSI_IntCtrl_0_ADDR:	0x106
BYTE			MOSI_IntCtrl_0_ADDR;
#pragma	ioport	MOSI_IntCtrl_1_ADDR:	0x107
BYTE			MOSI_IntCtrl_1_ADDR;
#pragma	ioport	MOSI_IntEn_ADDR:	0x5
BYTE			MOSI_IntEn_ADDR;
#define MOSI_MASK 0x80
#pragma	ioport	MOSI_MUXBusCtrl_ADDR:	0x1d9
BYTE			MOSI_MUXBusCtrl_ADDR;
// RST address and mask defines
#pragma	ioport	RST_Data_ADDR:	0x8
BYTE			RST_Data_ADDR;
#pragma	ioport	RST_DriveMode_0_ADDR:	0x108
BYTE			RST_DriveMode_0_ADDR;
#pragma	ioport	RST_DriveMode_1_ADDR:	0x109
BYTE			RST_DriveMode_1_ADDR;
#pragma	ioport	RST_DriveMode_2_ADDR:	0xb
BYTE			RST_DriveMode_2_ADDR;
#pragma	ioport	RST_GlobalSelect_ADDR:	0xa
BYTE			RST_GlobalSelect_ADDR;
#pragma	ioport	RST_IntCtrl_0_ADDR:	0x10a
BYTE			RST_IntCtrl_0_ADDR;
#pragma	ioport	RST_IntCtrl_1_ADDR:	0x10b
BYTE			RST_IntCtrl_1_ADDR;
#pragma	ioport	RST_IntEn_ADDR:	0x9
BYTE			RST_IntEn_ADDR;
#define RST_MASK 0x20
#pragma	ioport	RST_MUXBusCtrl_ADDR:	0x1da
BYTE			RST_MUXBusCtrl_ADDR;