📄 dongle.lst
字号:
02BA: FF 61 INDEX 0x021D
02BC: 00 SWI
02BD: 69 00 ASR [X+0]
02BF: 60 00 MOV REG[0],A
02C1: 62 00 67 MOV REG[0],103
02C4: 33 68 XOR A,[X+104]
02C6: 00 SWI
02C7: 63 00 66 MOV REG[X+0],102
02CA: 00 SWI
02CB: 64 ASL A
02CC: 00 SWI
02CD: 64 ASL A
02CE: 00 SWI
02CF: FD 80 INDEX 0x0051
02D1: C4 00 JC 0x06D2
02D3: C5 00 JC 0x07D4
02D5: C6 00 JC 0x08D6
02D7: C7 00 JC 0x09D8
02D9: D1 00 JNC 0x03DA
02DB: D3 00 JNC 0x05DC
02DD: D0 00 JNC 0x02DE
02DF: D2 00 JNC 0x04E0
02E1: E1 55 JACC 0x0437
02E3: E2 00 JACC 0x04E4
02E5: DF 13 JNC 0x01F9
02E7: DE 00 JNC 0x00E8
02E9: DD 00 JNC 0xFFEA
02EB: D8 00 JNC 0xFAEC
02ED: D9 00 JNC 0xFBEE
02EF: DA 00 JNC 0xFCF0
02F1: DB 00 JNC 0xFDF2
02F3: EC 00 JACC 0xFEF4
02F5: ED 00 JACC 0xFFF6
02F7: E7 00 JACC 0x09F8
02F9: C1 00 JC 0x03FA
02FB: 28 ROMX
02FC: 06 29 D5 ADD [41],213
02FF: 2A 67 OR A,[103]
0301: FF 08 INDEX 0x020B
0303: D5 7C JNC 0x0880
FILE: lib\psocconfig.asm
(0001) ; Generated by PSoC Designer ver 4.4 b1884 : 14 Jan, 2007
(0002) ;
(0003) ;==========================================================================
(0004) ; PSoCConfig.asm
(0005) ; @PSOC_VERSION
(0006) ;
(0007) ; Version: 0.85
(0008) ; Revised: June 22, 2004
(0009) ; Copyright Cypress MicroSystems 2000-2004. All Rights Reserved.
(0010) ;
(0011) ; This file is generated by the Device Editor on Application Generation.
(0012) ; It contains code which loads the configuration data table generated in
(0013) ; the file PSoCConfigTBL.asm
(0014) ;
(0015) ; DO NOT EDIT THIS FILE MANUALLY, AS IT IS OVERWRITTEN!!!
(0016) ; Edits to this file will not be preserved.
(0017) ;==========================================================================
(0018) ;
(0019) include "m8c.inc"
(0020) include "memory.inc"
(0021) include "GlobalParams.inc"
(0022)
(0023) export LoadConfigInit
(0024) export _LoadConfigInit
(0025) export LoadConfig_dongle
(0026) export _LoadConfig_dongle
(0027)
(0028) export NO_SHADOW
(0029) export _NO_SHADOW
(0030)
(0031) FLAG_CFG_MASK: equ 10h ;M8C flag register REG address bit mask
(0032) END_CONFIG_TABLE: equ ffh ;end of config table indicator
(0033)
(0034) AREA psoc_config(rom, rel)
(0035)
(0036) ;---------------------------------------------------------------------------
(0037) ; LoadConfigInit - Establish the start-up configuration (except for a few
(0038) ; parameters handled by boot code, like CPU speed). This
(0039) ; function can be called from user code, but typically it
(0040) ; is only called from boot.
(0041) ;
(0042) ; INPUTS: None.
(0043) ; RETURNS: Nothing.
(0044) ; SIDE EFFECTS: Registers are volatile: the A and X registers can be modified!
(0045) ; In the large memory model currently only the page
(0046) ; pointer registers listed below are modified. This does
(0047) ; not guarantee that in future implementations of this
(0048) ; function other page pointer registers will not be
(0049) ; modified.
(0050) ;
(0051) ; Page Pointer Registers Modified:
(0052) ; CUR_PP
(0053) ;
(0054) _LoadConfigInit:
(0055) LoadConfigInit:
(0056) RAM_PROLOGUE RAM_USE_CLASS_4
(0057)
0305: 01 A0 ADD A,160 (0058) lcall LoadConfigTBL_dongle_Ordered
0307: 7C 03 0B LCALL 0x030B (0059) lcall LoadConfig_dongle
(0060)
(0061)
(0062) RAM_EPILOGUE RAM_USE_CLASS_4
030A: 7F RET (0063) ret
(0064)
(0065) ;---------------------------------------------------------------------------
(0066) ; Load Configuration dongle
(0067) ;
(0068) ; Load configuration registers for dongle.
(0069) ; IO Bank 0 registers a loaded first,then those in IO Bank 1.
(0070) ;
(0071) ; INPUTS: None.
(0072) ; RETURNS: Nothing.
(0073) ; SIDE EFFECTS: Registers are volatile: the CPU A and X registers may be
(0074) ; modified as may the Page Pointer registers!
(0075) ; In the large memory model currently only the page
(0076) ; pointer registers listed below are modified. This does
(0077) ; not guarantee that in future implementations of this
(0078) ; function other page pointer registers will not be
(0079) ; modified.
(0080) ;
(0081) ; Page Pointer Registers Modified:
(0082) ; CUR_PP
(0083) ;
(0084) _LoadConfig_dongle:
(0085) LoadConfig_dongle:
(0086) RAM_PROLOGUE RAM_USE_CLASS_4
(0087)
030B: 10 PUSH X (0088) push x
030C: 70 EF AND F,239 (0089) M8C_SetBank0 ; Force bank 0
030E: 50 00 MOV A,0 (0090) mov a, 0 ; Specify bank 0
0310: 67 ASR A (0091) asr a ; Store in carry flag
(0092) ; Load bank 0 table:
0311: 50 02 MOV A,2 (0093) mov A, >LoadConfigTBL_dongle_Bank0
0313: 57 6C MOV X,108 (0094) mov X, <LoadConfigTBL_dongle_Bank0
0315: 7C 03 26 LCALL 0x0326 (0095) lcall LoadConfig ; Load the bank 0 values
(0096)
0318: 50 01 MOV A,1 (0097) mov a, 1 ; Specify bank 1
031A: 67 ASR A (0098) asr a ; Store in carry flag
(0099) ; Load bank 1 table:
031B: 50 02 MOV A,2 (0100) mov A, >LoadConfigTBL_dongle_Bank1
031D: 57 BB MOV X,187 (0101) mov X, <LoadConfigTBL_dongle_Bank1
031F: 7C 03 26 LCALL 0x0326 (0102) lcall LoadConfig ; Load the bank 1 values
(0103)
0322: 70 EF AND F,239 (0104) M8C_SetBank0 ; Force return to bank 0
0324: 20 POP X (0105) pop x
(0106)
(0107) RAM_EPILOGUE RAM_USE_CLASS_4
0325: 7F RET (0108) ret
(0109)
(0110)
(0111)
(0112)
(0113) ;---------------------------------------------------------------------------
(0114) ; LoadConfig - Set IO registers as specified in ROM table of (address,value)
(0115) ; pairs. Terminate on address=0xFF.
(0116) ;
(0117) ; INPUTS: [A,X] points to the table to be loaded
(0118) ; Flag Register Carry bit encodes the Register Bank
(0119) ; (Carry=0 => Bank 0; Carry=1 => Bank 1)
(0120) ;
(0121) ; RETURNS: nothing.
(0122) ;
(0123) ; STACK FRAME: X-4 I/O Bank 0/1 indicator
(0124) ; X-3 Temporary store for register address
(0125) ; X-2 LSB of config table address
(0126) ; X-1 MSB of config table address
(0127) ;
(0128) LoadConfig:
(0129) RAM_PROLOGUE RAM_USE_CLASS_2
0326: 38 02 ADD SP,2 (0130) add SP, 2 ; Set up local vars
0328: 10 PUSH X (0131) push X ; Save config table address on stack
0329: 08 PUSH A (0132) push A
032A: 4F MOV X,SP (0133) mov X, SP
032B: 56 FC 00 MOV [X-4],0 (0134) mov [X-4], 0 ; Set default Destination to Bank 0
032E: D0 04 JNC 0x0333 (0135) jnc .BankSelectSaved ; Carry says Bank 0 is OK
0330: 56 FC 01 MOV [X-4],1 (0136) mov [X-4], 1 ; No Carry: default to Bank 1
(0137) .BankSelectSaved:
0333: 18 POP A (0138) pop A
0334: 20 POP X (0139) pop X
(0140)
(0141) LoadConfigLp:
0335: 70 EF AND F,239 (0142) M8C_SetBank0 ; Switch to bank 0
0337: 62 E3 00 MOV REG[227],0 (0143) M8C_ClearWDT ; Clear the watchdog for long inits
033A: 10 PUSH X (0144) push X ; Preserve the config table address
033B: 08 PUSH A (0145) push A
033C: 28 ROMX (0146) romx ; Load register address from table
033D: 39 FF CMP A,255 (0147) cmp A, END_CONFIG_TABLE ; End of table?
033F: A0 1F JZ 0x035F (0148) jz EndLoadConfig ; Yes, go wrap it up
0341: 4F MOV X,SP (0149) mov X, SP ;
0342: 48 FC 01 TST [X-4],1 (0150) tst [X-4], 1 ; Loading IO Bank 1?
0345: A0 03 JZ 0x0349 (0151) jz .IOBankNowSet ; No, Bank 0 is fine
0347: 71 10 OR F,16 (0152) M8C_SetBank1 ; Yes, switch to Bank 1
(0153) .IOBankNowSet:
0349: 54 FD MOV [X-3],A (0154) mov [X-3], A ; Stash the register address
034B: 18 POP A (0155) pop A ; Retrieve the table address
034C: 20 POP X (0156) pop X
034D: 75 INC X (0157) inc X ; Advance to the data byte
034E: 09 00 ADC A,0 (0158) adc A, 0
0350: 10 PUSH X (0159) push X ; Save the config table address again
0351: 08 PUSH A (0160) push ⌨️ 快捷键说明
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