📄 dongle.lst
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00B8: 28 ROMX (0321) romx ; get the LSB of xidata's address
00B9: 4B SWAP A,X (0322) swap A, X
00BA: 51 21 MOV A,[33] (0323) mov A, [__r0] ; pXIData (in [A,X]) points to the
(0324) ; XIData structure list in flash
00BC: 80 04 JMP 0x00C1 (0325) jmp .AccessStruct
(0326)
(0327) ; Unpack one element in the xidata "structure list" that specifies the
(0328) ; values of C variables. Each structure contains 3 member elements.
(0329) ; The first is a pointer to a contiguous block of RAM to be initial-
(0330) ; ized. Blocks are always 255 bytes or less in length and never cross
(0331) ; RAM page boundaries. The list terminates when the MSB of the pointer
(0332) ; contains 0xFF. There are two formats for the struct depending on the
(0333) ; value in the second member element, an unsigned byte:
(0334) ; (1) If the value of the second element is non-zero, it represents
(0335) ; the 'size' of the block of RAM to be initialized. In this case, the
(0336) ; third member of the struct is an array of bytes of length 'size' and
(0337) ; the bytes are copied to the block of RAM.
(0338) ; (2) If the value of the second element is zero, the block of RAM is
(0339) ; to be cleared to zero. In this case, the third member of the struct
(0340) ; is an unsigned byte containing the number of bytes to clear.
(0341)
(0342) .AccessNextStructLoop:
00BE: 75 INC X (0343) inc X ; pXIData++
00BF: 09 00 ADC A,0 (0344) adc A, 0
(0345) .AccessStruct: ; Entry point for first block
(0346) ;
(0347) ; Assert: pXIData in [A,X] points to the beginning of an XIData struct.
(0348) ;
00C1: 62 E3 00 MOV REG[227],0 (0349) M8C_ClearWDT ; Clear the watchdog for long inits
00C4: 08 PUSH A (0350) push A
00C5: 28 ROMX (0351) romx ; MSB of RAM addr (CPU.A <- *pXIData)
00C6: 60 D5 MOV REG[213],A (0352) mov reg[MVW_PP], A ; for use with MVI write operations
00C8: 74 INC A (0353) inc A ; End of Struct List? (MSB==0xFF?)
00C9: A0 4B JZ 0x0115 (0354) jz .C_RTE_WrapUp ; Yes, C runtime environment complete
00CB: 18 POP A (0355) pop A ; restore pXIData to [A,X]
00CC: 75 INC X (0356) inc X ; pXIData++
00CD: 09 00 ADC A,0 (0357) adc A, 0
00CF: 08 PUSH A (0358) push A
00D0: 28 ROMX (0359) romx ; LSB of RAM addr (CPU.A <- *pXIData)
00D1: 53 21 MOV [__r0],A (0360) mov [__r0], A ; RAM Addr now in [reg[MVW_PP],[__r0]]
00D3: 18 POP A (0361) pop A ; restore pXIData to [A,X]
00D4: 75 INC X (0362) inc X ; pXIData++ (point to size)
00D5: 09 00 ADC A,0 (0363) adc A, 0
00D7: 08 PUSH A (0364) push A
00D8: 28 ROMX (0365) romx ; Get the size (CPU.A <- *pXIData)
00D9: A0 1C JZ 0x00F6 (0366) jz .ClearRAMBlockToZero ; If Size==0, then go clear RAM
00DB: 53 20 MOV [__r1],A (0367) mov [__r1], A ; else downcount in __r1
00DD: 18 POP A (0368) pop A ; restore pXIData to [A,X]
(0369)
(0370) .CopyNextByteLoop:
(0371) ; For each byte in the structure's array member, copy from flash to RAM.
(0372) ; Assert: pXIData in [A,X] points to previous byte of flash source;
(0373) ; [reg[MVW_PP],[__r0]] points to next RAM destination;
(0374) ; __r1 holds a non-zero count of the number of bytes remaining.
(0375) ;
00DE: 75 INC X (0376) inc X ; pXIData++ (point to next data byte)
00DF: 09 00 ADC A,0 (0377) adc A, 0
00E1: 08 PUSH A (0378) push A
00E2: 28 ROMX (0379) romx ; Get the data value (CPU.A <- *pXIData)
00E3: 3F 21 MVI [__r0],A (0380) mvi [__r0], A ; Transfer the data to RAM
00E5: 47 21 FF TST [33],255 (0381) tst [__r0], 0xff ; Check for page crossing
00E8: B0 06 JNZ 0x00EF (0382) jnz .CopyLoopTail ; No crossing, keep going
00EA: 5D D5 MOV A,REG[213] (0383) mov A, reg[ MVW_PP] ; If crossing, bump MVW page reg
00EC: 74 INC A (0384) inc A
00ED: 60 D5 MOV REG[213],A (0385) mov reg[ MVW_PP], A
(0386) .CopyLoopTail:
00EF: 18 POP A (0387) pop A ; restore pXIData to [A,X]
00F0: 7A 20 DEC [__r1] (0388) dec [__r1] ; End of this array in flash?
00F2: BF EB JNZ 0x00DE (0389) jnz .CopyNextByteLoop ; No, more bytes to copy
00F4: 8F C9 JMP 0x00BE (0390) jmp .AccessNextStructLoop ; Yes, initialize another RAM block
(0391)
(0392) .ClearRAMBlockToZero:
00F6: 18 POP A (0393) pop A ; restore pXIData to [A,X]
00F7: 75 INC X (0394) inc X ; pXIData++ (point to next data byte)
00F8: 09 00 ADC A,0 (0395) adc A, 0
00FA: 08 PUSH A (0396) push A
00FB: 28 ROMX (0397) romx ; Get the run length (CPU.A <- *pXIData)
00FC: 53 20 MOV [__r1],A (0398) mov [__r1], A ; Initialize downcounter
00FE: 50 00 MOV A,0 (0399) mov A, 0 ; Initialize source data
(0400)
(0401) .ClearRAMBlockLoop:
(0402) ; Assert: [reg[MVW_PP],[__r0]] points to next RAM destination and
(0403) ; __r1 holds a non-zero count of the number of bytes remaining.
(0404) ;
0100: 3F 21 MVI [__r0],A (0405) mvi [__r0], A ; Clear a byte
0102: 47 21 FF TST [33],255 (0406) tst [__r0], 0xff ; Check for page crossing
0105: B0 08 JNZ 0x010E (0407) jnz .ClearLoopTail ; No crossing, keep going
0107: 5D D5 MOV A,REG[213] (0408) mov A, reg[ MVW_PP] ; If crossing, bump MVW page reg
0109: 74 INC A (0409) inc A
010A: 60 D5 MOV REG[213],A (0410) mov reg[ MVW_PP], A
010C: 50 00 MOV A,0 (0411) mov A, 0 ; Restore the zero used for clearing
(0412) .ClearLoopTail:
010E: 7A 20 DEC [__r1] (0413) dec [__r1] ; Was this the last byte?
0110: BF EF JNZ 0x0100 (0414) jnz .ClearRAMBlockLoop ; No, continue
0112: 18 POP A (0415) pop A ; Yes, restore pXIData to [A,X] and
0113: 8F AA JMP 0x00BE (0416) jmp .AccessNextStructLoop ; initialize another RAM block
(0417)
(0418) .C_RTE_WrapUp:
0115: 18 POP A (0419) pop A ; balance stack
(0420)
(0421) ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
(0422)
(0423) C_RTE_Done:
(0424)
(0425) ENDIF ; C_LANGUAGE_SUPPORT
(0426)
(0427)
(0428) ;-------------------------------
(0429) ; Set Power-On Reset (POR) Level
(0430) ;-------------------------------
0116: 71 10 OR F,16 (0431) M8C_SetBank1
(0432)
(0433) IF (POWER_SETTING & POWER_SET_3V3) ; 3.3V Operation?
(0434) or reg[VLT_CR], VLT_CR_POR_LOW ; Yes, change to midpoint trip
(0435) ELSE ; 5V Operation
(0436) IF ( CPU_CLOCK_JUST ^ OSC_CR0_CPU_24MHz ) ; As fast as 24MHz?
(0437) or reg[VLT_CR], VLT_CR_POR_LOW ; No, change to midpoint trip
(0438) ELSE ; 24HMz ;
0118: 43 E3 20 OR REG[227],32 (0439) or reg[VLT_CR], VLT_CR_POR_HIGH ; Yes, switch to highest setting
(0440) ENDIF ; 24MHz
(0441) ENDIF ; 3.3V Operation
(0442)
011B: 70 EF AND F,239 (0443) M8C_SetBank0
(0444)
(0445) ;----------------------------
(0446) ; Wrap up and invoke "main"
(0447) ;----------------------------
(0448)
(0449) ; Disable the Sleep interrupt that was used for timing above. In fact,
(0450) ; no interrupts should be enabled now, so may as well clear the register.
(0451) ;
011D: 62 E0 00 MOV REG[224],0 (0452) mov reg[INT_MSK0],0
(0453)
(0454) ; Everything has started OK. Now select requested CPU & sleep frequency.
(0455) ;
0120: 71 10 OR F,16 (0456) M8C_SetBank1
0122: 62 E0 03 MOV REG[224],3 (0457) mov reg[OSC_CR0],(SLEEP_TIMER_JUST | CPU_CLOCK_JUST)
0125: 70 EF AND F,239 (0458) M8C_SetBank0
(0459)
(0460) ; Global Interrupt are NOT enabled, this should be done in main().
(0461) ; LVD is set but will not occur unless Global Interrupts are enabled.
(0462) ; Global Interrupts should be enabled as soon as possible in main().
(0463) ;
0127: 62 E2 00 MOV REG[226],0 (0464) mov reg[INT_VC],0 ; Clear any pending interrupts which may
(0465) ; have been set during the boot process.
(0466) IF ENABLE_LJMP_TO_MAIN
(0467) ljmp _main ; goto main (no return)
(0468) ELSE
012A: 7C 07 F3 LCALL _main (0469) lcall _main ; call main
(0470) .Exit:
012D: 8F FF JMP 0x012D (0471) jmp .Exit ; Wait here after return till power-off or reset
(0472) ENDIF
(0473)
(0474) ;---------------------------------
(0475) ; Library Access to Global Parms
(0476) ;---------------------------------
(0477) ;
(0478) bGetPowerSetting:
(0479) _bGetPowerSetting:
(0480) ; Returns value of POWER_SETTING in the A register.
(0481) ; No inputs. No Side Effects.
(0482) ;
012F: 50 10 MOV A,16 (0483) mov A, POWER_SETTING ; Supply voltage and internal main osc
0131: 7F RET (0484) ret
0132: 30 HALT
0133: 30 HALT
0134: 30 HALT
0135: 30 HALT
0136: 30 HALT
0137: 30 HALT
0138: 30 HALT
0139: 30 HALT
013A: 30 HALT
013B: 30 HALT
013C: 30 HALT
013D: 30 HALT
013E: 30 HALT
013F: 30 HALT
0140: 30 HALT
0141: 30 HALT
0142: 30 HALT
0143: 30 HALT
0144: 30 HALT
0145: 30 HALT
0146: 30 HALT
0147: 30 HALT
0148: 30 HALT
0149: 30 HALT
014A: 30 HALT
014B: 30 HALT
014C: 30 HALT
014D: 30 HALT
014E: 30 HALT
014F: 30 HALT
0150: 30 HALT
0151: 30 HALT
0152: 30 HALT
0153: 30 HALT
0154: 30 HALT
0155: 30 HALT
0156: 30 HALT
0157: 30 HALT
0158: 30 HALT
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