📄 lpradio.lis
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0000
0000
0000 ; -------------------------------
0000 ; RX Length Field register
0000 ; -------------------------------
000A RX_LENGTH_ADR: equ 0x0a
0000 RX_LENGTH_RST: equ 0x00
00FF RX_LENGTH_MSK: equ 0xff
0000
0000
0000 ; -------------------------------
0000 ; Power Control register
0000 ; -------------------------------
000B PWR_CTRL_ADR: equ 0x0b
00A0 PWR_CTRL_RST: equ 0xa0
0000
0000 ; single flag bits & multi-bit-field masks
0080 PMU_EN: equ 0x80
0040 LV_IRQ_EN: equ 0x40
0020 PMU_SEN: equ 0x20
0010 PFET_OFF: equ 0x10
000C LV_IRQ_TH_MSK: equ 0x0c
0003 PMU_OUTV_MSK: equ 0x03
0000
0000 ; LV_IRQ_TH values
000C LV_IRQ_TH_1P8_V: equ 0x0C
0008 LV_IRQ_TH_2P0_V: equ 0x08
0004 LV_IRQ_TH_2P2_V: equ 0x04
0000 LV_IRQ_TH_PMU_OUTV: equ 0x00
0000
0000 ; PMU_OUTV values
0003 PMU_OUTV_2P4: equ 0x03
0002 PMU_OUTV_2P5: equ 0x02
0001 PMU_OUTV_2P6: equ 0x01
0000 PMU_OUTV_2P7: equ 0x00
0000
0000
0000 ; -------------------------------
0000 ; Crystal Control register
0000 ; -------------------------------
000C XTAL_CTRL_ADR: equ 0x0c
0004 XTAL_CTRL_RST: equ 0x04
0000
0000 ; single flag bits & multi-bit-field masks
00C0 XOUT_FNC_MSK: equ 0xc0
0020 XS_IRQ_EN: equ 0x20
0007 XOUT_FREQ_MSK: equ 0x07
0000
0000 ; XOUT_FNC values
0000 XOUT_FNC_XOUT_FREQ: equ 0x00
0040 XOUT_FNC_PA_N: equ 0x40
0080 XOUT_FNC_RAD_STREAM: equ 0x80
00C0 XOUT_FNC_GPIO: equ 0xC0
0000
0000 ; XOUT_FREQ values
0000 XOUT_FREQ_12MHZ: equ 0x00
0001 XOUT_FREQ_6MHZ: equ 0x01
0002 XOUT_FREQ_3MHZ: equ 0x02
0003 XOUT_FREQ_1P5MHZ: equ 0x03
0004 XOUT_FREQ_P75MHZ: equ 0x04
0000
0000
0000 ; -------------------------------
0000 ; I/O Configuration register
0000 ; -------------------------------
000D IO_CFG_ADR: equ 0x0d
0000 IO_CFG_RST: equ 0x00
00FF IO_CFG_MSK: equ 0xff
0000
0000 ; single flag bits & multi-bit-field masks
0080 IRQ_OD: equ 0x80
0040 IRQ_POL: equ 0x40
0020 MISO_OD: equ 0x20
0010 XOUT_OD: equ 0x10
0008 PACTL_OD: equ 0x08
0004 PACTL_GPIO: equ 0x04
0002 SPI_3_PIN: equ 0x02
0001 IRQ_GPIO: equ 0x01
0000
0000
0000 ; -------------------------------
0000 ; GPIO Control register
0000 ; -------------------------------
000E GPIO_CTRL_ADR: equ 0x0e
0000 GPIO_CTRL_RST: equ 0x00
00F0 GPIO_CTRL_MSK: equ 0xf0
0000
0000 ; single flag bits & multi-bit-field masks
0080 XOUT_OP: equ 0x80
0040 MISO_OP: equ 0x40
0020 PACTL_OP: equ 0x20
0010 IRQ_OP: equ 0x10
0008 XOUT_IP: equ 0x08
0004 MISO_IP: equ 0x04
0002 PACTL_IP: equ 0x02
0001 IRQ_IP: equ 0x01
0000
0000
0000 ; -------------------------------
0000 ; Transaction Configuration register
0000 ; -------------------------------
000F XACT_CFG_ADR: equ 0x0f
0080 XACT_CFG_RST: equ 0x80
0000
0000 ; single flag bits & multi-bit-field masks
0080 ACK_EN: equ 0x80
0020 FRC_END_STATE: equ 0x20
001C END_STATE_MSK: equ 0x1c
0003 ACK_TO_MSK: equ 0x03
0000
0000 ; END_STATE field values
0000 END_STATE_SLEEP: equ 0x00
0004 END_STATE_IDLE: equ 0x04
0008 END_STATE_TXSYNTH: equ 0x08
000C END_STATE_RXSYNTH: equ 0x0C
0010 END_STATE_RX: equ 0x10
0000
0000 ; ACK_TO field values
0000 ACK_TO_4X: equ 0x00
0001 ACK_TO_8X: equ 0x01
0002 ACK_TO_12X: equ 0x02
0003 ACK_TO_15X: equ 0x03
0000
0000
0000 ; -------------------------------
0000 ; Framing Configuration register
0000 ; -------------------------------
0010 FRAMING_CFG_ADR: equ 0x10
00A5 FRAMING_CFG_RST: equ 0xa5
0000
0000 ; single flag bits & multi-bit-field masks
0080 SOP_EN: equ 0x80
0040 SOP_LEN: equ 0x40
0020 LEN_EN: equ 0x20
001F SOP_THRESH_MSK: equ 0x1f
0000
0000
0000 ; -------------------------------
0000 ; Data Threshold 32 register
0000 ; -------------------------------
0011 DATA32_THOLD_ADR: equ 0x11
0004 DAT32_THRESH_RST: equ 0x04
000F DAT32_THRESH_MSK: equ 0x0f
0000
0000
0000 ; -------------------------------
0000 ; Data Threshold 64 register
0000 ; -------------------------------
0012 DATA64_THOLD_ADR: equ 0x12
000A DAT64_THRESH_RST: equ 0x0a
001F DAT64_THRESH_MSK: equ 0x1f
0000
0000
0000 ; -------------------------------
0000 ; RSSI register
0000 ; -------------------------------
0013 RSSI_ADR: equ 0x13
0020 RSSI_RST: equ 0x20
0000
0000 ; single flag bits & multi-bit-field masks
0080 SOP_RSSI: equ 0x80
0020 LNA_STATE: equ 0x20
001F RSSI_LVL_MSK: equ 0x1f
0000
0000
0000 ; -------------------------------
0000 ; EOP Control register
0000 ; -------------------------------
0014 EOP_CTRL_ADR: equ 0x14
00A4 EOP_CTRL_RST: equ 0xa4
0000
0000 ; single flag bits & multi-bit-field masks
0080 HINT_EN: equ 0x80
0070 HINT_EOP_MSK: equ 0x70
000F EOP_MSK: equ 0x0f
0000
0000
0000 ; -------------------------------
0000 ; CRC Seed registers
0000 ; -------------------------------
0015 CRC_SEED_LSB_ADR: equ 0x15
0016 CRC_SEED_MSB_ADR: equ 0x16
0000 CRC_SEED_LSB_RST: equ 0x00
0000 CRC_SEED_MSB_RST: equ 0x00
0000
0000 ; CRC related values
0000 ; USB CRC-16
0080 CRC_POLY_MSB: equ 0x80
0005 CRC_POLY_LSB: equ 0x05
0080 CRC_RESI_MSB: equ 0x80
000D CRC_RESI_LSB: equ 0x0d
0000
0000
0000 ; -------------------------------
0000 ; TX CRC Calculated registers
0000 ; -------------------------------
0017 TX_CRC_LSB_ADR: equ 0x17
0018 TX_CRC_MSB_ADR: equ 0x18
0000
0000
0000 ; -------------------------------
0000 ; RX CRC Field registers
0000 ; -------------------------------
0019 RX_CRC_LSB_ADR: equ 0x19
001A RX_CRC_MSB_ADR: equ 0x1a
00FF RX_CRC_LSB_RST: equ 0xff
00FF RX_CRC_MSB_RST: equ 0xff
0000
0000
0000 ; -------------------------------
0000 ; Synth Offset registers
0000 ; -------------------------------
001B TX_OFFSET_LSB_ADR: equ 0x1b
001C TX_OFFSET_MSB_ADR: equ 0x1c
0000 TX_OFFSET_LSB_RST: equ 0x00
0000 TX_OFFSET_MSB_RST: equ 0x00
0000
0000 ; single flag bits & multi-bit-field masks
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