📄 lpradio.lst
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421
422 0000 FRC_AWAKE: equ 0x03
423 0000 FRC_AWAKE_OFF_1: equ 0x01
424 0000 FRC_AWAKE_OFF_2: equ 0x00
425
426 ; single flag bits & multi-bit-field masks
427 0000 DIS_AUTO_SEN: equ 0x80
428 0000 SEN_TXRXB: equ 0x40
429 0000 FRC_SEN: equ 0x20
430 0000 FRC_AWAKE_MSK: equ 0x18
431 0000 MODE_OVRD_FRC_AWAKE: equ 0x18
432 0000 MODE_OVRD_FRC_AWAKE_OFF_1: equ 0x08
433 0000 MODE_OVRD_FRC_AWAKE_OFF_2: equ 0x00
434 0000 RST: equ 0x01
435 0000 FRC_PA: equ 0x02
436
437
438 ; -------------------------------
439 ; RX Override register
440 ; -------------------------------
441 0000 RX_OVERRIDE_ADR: equ 0x1e
442 0000 RX_OVERRIDE_RST: equ 0x00
443
444 ; single flag bits & multi-bit-field masks
445 0000 ACK_RX: equ 0x80
446 0000 EXTEND_RX_TX: equ 0x40
447 0000 MAN_RXACK: equ 0x20
448 0000 FRC_RXDR: equ 0x10
449 0000 DIS_CRC0: equ 0x08
450 0000 DIS_RXCRC: equ 0x04
451 0000 ACE: equ 0x02
452
453
454 ; -------------------------------
455 ; TX Override register
456 ; -------------------------------
457 0000 TX_OVERRIDE_ADR: equ 0x1f
458 0000 TX_OVERRIDE_RST: equ 0x00
459
460 ; single flag bits & multi-bit-field masks
461 0000 ACK_TX_SEN: equ 0x80
462 0000 FRC_PREAMBLE: equ 0x40
463 0000 DIS_TX_RETRANS: equ 0x20
464 0000 MAN_TXACK: equ 0x10
465 0000 OVRRD_ACK: equ 0x08
466 0000 DIS_TXCRC: equ 0x04
467 0000 CO: equ 0x02
468 0000 TXINV: equ 0x01
469
470
471 ;------------------------------------------------------------------------------
472 ; File Function Detail
473 ;------------------------------------------------------------------------------
474
475 ; -------------------------------
476 ; TX Buffer - 16 bytes
477 ; -------------------------------
478 0000 TX_BUFFER_ADR: equ 0x20
479
480
481 ; -------------------------------
482 ; RX Buffer - 16 bytes
483 ; -------------------------------
484 0000 RX_BUFFER_ADR: equ 0x21
485
486
487 ; -------------------------------
488 ; Framing Code - 8 bytes
489 ; -------------------------------
490 0000 SOP_CODE_ADR: equ 0x22
491
492 ; CODESTORE_REG_SOF_RST 64'h17_ff_9e_21_36_90_c7_82
493 0000 CODESTORE_BYTE7_SOF_RST: equ 0x17
494 0000 CODESTORE_BYTE6_SOF_RST: equ 0xff
495 0000 CODESTORE_BYTE5_SOF_RST: equ 0x9e
496 0000 CODESTORE_BYTE4_SOF_RST: equ 0x21
497 0000 CODESTORE_BYTE3_SOF_RST: equ 0x36
498 0000 CODESTORE_BYTE2_SOF_RST: equ 0x90
499 0000 CODESTORE_BYTE1_SOF_RST: equ 0xc7
500 0000 CODESTORE_BYTE0_SOF_RST: equ 0x82
501
502
503 ; -------------------------------
504 ; Data Code - 16 bytes
505 ; -------------------------------
506 0000 DATA_CODE_ADR: equ 0x23
507
508 ; CODESTORE_REG_DCODE0_RST 64'h01_2B_F1_DB_01_32_BE_6F
509 0000 CODESTORE_BYTE7_DCODE0_RST: equ 0x01
510 0000 CODESTORE_BYTE6_DCODE0_RST: equ 0x2b
511 0000 CODESTORE_BYTE5_DCODE0_RST: equ 0xf1
512 0000 CODESTORE_BYTE4_DCODE0_RST: equ 0xdb
513 0000 CODESTORE_BYTE3_DCODE0_RST: equ 0x01
514 0000 CODESTORE_BYTE2_DCODE0_RST: equ 0x32
515 0000 CODESTORE_BYTE1_DCODE0_RST: equ 0xbe
516 0000 CODESTORE_BYTE0_DCODE0_RST: equ 0x6f
517
518 ; CODESTORE_REG_DCODE1_RST 64'h02_F9_93_97_02_FA_5C_E3
519 0000 CODESTORE_BYTE7_DCODE1_RST: equ 0x02
520 0000 CODESTORE_BYTE6_DCODE1_RST: equ 0xf9
521 0000 CODESTORE_BYTE5_DCODE1_RST: equ 0x93
522 0000 CODESTORE_BYTE4_DCODE1_RST: equ 0x97
523 0000 CODESTORE_BYTE3_DCODE1_RST: equ 0x02
524 0000 CODESTORE_BYTE2_DCODE1_RST: equ 0xfa
525 0000 CODESTORE_BYTE1_DCODE1_RST: equ 0x5c
526 0000 CODESTORE_BYTE0_DCODE1_RST: equ 0xe3
527
528
529 ; -------------------------------
530 ; Preamble - 3 bytes
531 ; -------------------------------
532 0000 PREAMBLE_ADR: equ 0x24
533
534 0000 PREAMBLE_CODE_MSB_RST: equ 0x33
535 0000 PREAMBLE_CODE_LSB_RST: equ 0x33
536 0000 PREAMBLE_LEN_RST: equ 0x02
537
538
539 ; -------------------------------
540 ; Laser Fuses - 8 bytes (2 hidden)
541 ; -------------------------------
542 0000 MFG_ID_ADR: equ 0x25
543
544
545 ; -------------------------------
546 ; XTAL Startup Delay
547 ; -------------------------------
548 0000 XTAL_CFG_ADR: equ 0x26
549 0000 XTAL_CFG_RST: equ 0x00
550
551 ; -------------------------------
552 ; Clock Override
553 ; -------------------------------
554 0000 CLK_OVERRIDE_ADR: equ 0x27
555 0000 CLK_OVERRIDE_RST: equ 0x00
556
557 0000 RXF: equ 0x02
558
559
560 ; -------------------------------
561 ; Clock Enable
562 ; -------------------------------
563 0000 CLK_EN_ADR: equ 0x28
564 0000 CLK_EN_RST: equ 0x00
565
566 0000 RXF: equ 0x02
567
568
569 ; -------------------------------
570 ; Receiver Abort
571 ; -------------------------------
572 0000 RX_ABORT_ADR: equ 0x29
573 0000 RX_ABORT_RST: equ 0x00
574
575 0000 ABORT_EN: equ 0x20
576
577
578 ; -------------------------------
579 ; Auto Calibration Time
580 ; -------------------------------
581 0000 AUTO_CAL_TIME_ADR: equ 0x32
582 0000 AUTO_CAL_TIME_RST: equ 0x0C
583
584 0000 AUTO_CAL_TIME_MAX: equ 0x3C
585
586
587 ; -------------------------------
588 ; Auto Calibration Offset
589 ; -------------------------------
590 0000 AUTO_CAL_OFFSET_ADR: equ 0x35
591 0000 AUTO_CAL_OFFSET_RST: equ 0x00
592
593 0000 AUTO_CAL_OFFSET_MINUS_4: equ 0x14
1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2 ;;;
3 ;;; M8C.INC -- CY7C64215 Microcontroller Device System Declarations
4 ;;;
5 ;;; Copyright (c) 2005 Cypress Semiconductor, Inc. All rights reserved.
6 ;;;
7 ;;;
8 ;;; This file provides add⌨️ 快捷键说明
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